View MC912D60PVFU8_6967875.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

hc12 microcontrollers freescale.com mc68hc912d60a mc68hc912d60c mc68hc912d60p technical data mc68hc912d60a/d rev. 3.1 08/2005

mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor 3 mc68hc912d60a mc68hc912d60c mc68hc912d60p technical data ? rev. 3.1 freescale reserves the right to make changes without further notice to any products herein. freescale makes no warranty, representation or guarantee regarding the suitability of its products fo r any particular pu rpose, nor does freescale assume any liability arising out of the app lication or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequ ential or incidental damages. "typical" parameters which may be provided in freescale data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including "typicals" must be validated for each customer application by customer's technical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale product could create a situation where personal injury or death may occur. should buyer purchase or use freescale products for any such unintended or unauthorized application, buyer shall indemnify and hold free scale and its officers, employ ees, subsidiaries, affiliates, and distributors harmless against all cl aims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintend ed or unauthorized use, even if such claim alleges that freescale was negligent regarding the design or manufacture of the part. freescale, inc. is an equal opportunity/affirmative action employer. ? freescale, inc., 2005
technical data mc68hc9 12d60a ? rev. 3.1 4 freescale semiconductor
mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor list of paragraphs 5 technical data ? mc68hc912d60a list of paragraphs list of paragraphs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 section 1. general description . . . . . . . . . . . . . . . . . . . . 23 section 2. central processing unit . . . . . . . . . . . . . . . . . 31 section 3. pinout and signal d escriptions . . . . . . . . . . . 37 section 4. registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 section 5. operating modes and resource mapping . . 71 section 6. bus control and input/ output . . . . . . . . . . . . 85 section 7. flash memory . . . . . . . . . . . . . . . . . . . . . . . . . 97 section 8. eeprom memory . . . . . . . . . . . . . . . . . . . . . 105 section 9. resets and in terrupts . . . . . . . . . . . . . . . . . . 119 section 10. i/o ports with key wa ke-up . . . . . . . . . . . . 129 section 11. clock functions . . . . . . . . . . . . . . . . . . . . . 137 section 12. oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 section 13. pulse width modulator . . . . . . . . . . . . . . . . 207 section 14. enhanced capture timer . . . . . . . . . . . . . . 223 section 15. multiple serial interf ace . . . . . . . . . . . . . . . 263 section 16. freescale interconnect bus . . . . . . . . . . . . 289
list of paragraphs technical data mc68hc9 12d60a ? rev. 3.1 6 list of paragraphs freescale semiconductor section 17. mscan controller. . . . . . . . . . . . . . . . . . . . 303 section 18. analog-to-d igital converter . . . . . . . . . . . . 349 section 19. development support. . . . . . . . . . . . . . . . . 377 section 20. electrical sp ecifications. . . . . . . . . . . . . . . 405 section 21. appendix: cgm pract ical aspects . . . . . . 427 section 22. appendix: chan ges from mc68hc912d60437 section 23. appendix: info rmation on mc68hc912d60a mask set changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor table of contents 7 technical data ? mc68hc912d60a table of contents technical data ? li st of paragraphs technical data ? table of contents technical data ? list of figures technical data ? list of tables section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.3 devices covered in this document. . . . . . . . . . . . . . . . . . . . . . 24 1.4 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.5 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.6 block diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 section 2. central processing unit 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.3 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.4 data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.5 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.6 indexed addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.7 opcodes and operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
table of contents technical data mc68hc9 12d60a ? rev. 3.1 8 table of contents freescale semiconductor section 3. pinout an d signal descriptions 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.2 mc68hc912d60a pin assignments in 112-pin qfp . . . . . . . . 38 3.3 mc68hc912d60a pin assignments in 80-pin qfp . . . . . . . . . 40 3.4 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.5 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.6 port signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 section 4. registers 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 4.2 register block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 section 5. operating modes and resource mapping 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.3 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.4 background debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.5 internal resource mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . .77 5.6 memory maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 section 6. bus control and input/output 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.3 detecting access type from external signals . . . . . . . . . . . . . 85 6.4 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 section 7. flash memory 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
table of contents mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor table of contents 9 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.3 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 7.4 flash eeprom control bl ock . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.5 flash eeprom arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.6 flash eeprom registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.7 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.8 programming the flash eep rom . . . . . . . . . . . . . . . . . . . . . 101 7.9 erasing the flash eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.10 stop or wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.11 flash protection bit fpop en . . . . . . . . . . . . . . . . . . . . . . . . . 104 section 8. eeprom memory 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.3 eeprom selective write more zeros . . . . . . . . . . . . . . . . . . 106 8.4 eeprom programmer? s model . . . . . . . . . . . . . . . . . . . . . . .107 8.5 eeprom control registers . . . . . . . . . . . . . . . . . . . . . . . . . . 108 8.6 program/erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.7 shadow word mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.8 programming eedivh and eedivl registers. . . . . . . . . . . . 116 section 9. resets and interrupts 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 9.3 maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 9.4 latching of interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.5 interrupt control and priority regist ers . . . . . . . . . . . . . . . . . 123
table of contents technical data mc68hc9 12d60a ? rev. 3.1 10 table of contents freescale semiconductor 9.6 resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.7 effects of reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9.8 register stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.9 customer information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 section 10. i/o port s with key wake-up 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 10.3 key wake-up and port r egisters . . . . . . . . . . . . . . . . . . . . . . 130 10.4 key wake-up input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 section 11. clock functions 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 11.3 clock sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 11.4 phase-locked loop (p ll) . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 11.5 acquisition and tracking modes. . . . . . . . . . . . . . . . . . . . . . . 141 11.6 limp-home and fast stop recove ry modes . . . . . . . . . . . . 143 11.7 system clock frequency formulas . . . . . . . . . . . . . . . . . . . . . 162 11.8 clock divider chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 11.9 computer operating prop erly (cop) . . . . . . . . . . . . . . . . . . . 166 11.10 real-time interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 11.11 clock monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167 11.12 clock function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 section 12. oscillator 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
table of contents mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor table of contents 11 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 12.3 mc68hc912d60a oscillator specification. . . . . . . . . . . . . . . 176 12.4 mc68hc912d60c colpitts oscillator specification . . . . . . . . 179 12.5 mc68hc912d60p pierce oscillator s pecification . . . . . . . . . 194 section 13. pulse width modulator 13.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 13.3 pwm register description . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 13.4 pwm boundary cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 section 14. enhanced capture timer 14.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 14.3 enhanced capture timer modes of operation . . . . . . . . . . . . 230 14.4 timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 14.5 timer and modulus counter operation in different modes . . 261 section 15. multiple serial interface 15.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 15.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 15.4 serial communication inte rface (sci) . . . . . . . . . . . . . . . . . . 264 15.5 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . 276 15.6 port s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 section 16. freescale interconnect bus 16.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289
table of contents technical data mc68hc9 12d60a ? rev. 3.1 12 table of contents freescale semiconductor 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 16.3 push-pull sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 16.4 biphase coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 16.5 message validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 16.6 interfacing to mi bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 16.7 mi bus clock rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 16.8 sci0/mi bus registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 section 17. mscan controller 17.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 17.3 external pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 17.4 message storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 17.5 identifier acceptance filter . . . . . . . . . . . . . . . . . . . . . . . . . . .310 17.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314 17.7 protocol violation protecti on. . . . . . . . . . . . . . . . . . . . . . . . . . 316 17.8 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 17.9 timer link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 17.10 clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321 17.11 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 17.12 programmer?s model of message storage . . . . . . . . . . . . . . . 325 17.13 programmer?s model of control registers . . . . . . . . . . . . . . . 330 section 18. analog-to-digital converter 18.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 18.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
table of contents mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor table of contents 13 18.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352 18.5 atd operational modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 18.6 atd operation in different mcu modes . . . . . . . . . . . . . . . . 355 18.7 general purpose digital input port operation . . . . . . . . . . . . 357 18.8 application considerations . . . . . . . . . . . . . . . . . . . . . . . . . . .358 18.9 atd registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 section 19. development support 19.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 19.3 instruction queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377 19.4 background debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 19.5 breakpoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 19.6 instruction tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 section 20. electrical specifications 20.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 20.3 tables of data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 section 21. appendix: cgm practical aspects 21.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427 21.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 21.3 practical aspects for the pll usage . . . . . . . . . . . . . . . . . . 427 21.4 printed circuit board gui delines. . . . . . . . . . . . . . . . . . . . . . . 433 section 22. appendix: ch anges from mc68hc912d60 22.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .437
table of contents technical data mc68hc9 12d60a ? rev. 3.1 14 table of contents freescale semiconductor 22.2 significant changes from the mc68hc912d60 (non-suffix device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 section 23. appendix: info rmation on mc68hc912d60a mask set changes 23.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .443 23.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 23.3 flash protection feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 23.4 clock circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 23.5 pseudo stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 23.6 oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .444 23.7 pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 technical data ? glossary technical data ? revision history 23.8 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .457 23.9 changes from rev 2.0 to rev 3.0 . . . . . . . . . . . . . . . . . . . . . 457 23.10 major changes from rev 1.0 to rev 2.0 . . . . . . . . . . . . . . . . 457 23.11 major changes from rev 0.0 to rev 1.0 . . . . . . . . . . . . . . . . 458
mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor list of figures 15 technical data ? mc68hc912d60a list of figures figure title page 1-1 mc68hc912d60a 112-pin qfp block diagram . . . . . . . . . . . 29 1-2 mc68hc912d60a 80-pin qfp block dia gram . . . . . . . . . . . . 30 2-1 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3-1 pin assignments in 112-pin tq fp for mc68hc912d60a . . . . 38 3-2 112-pin tqfp mechanical dimensi ons (case no987) . . . . . . . 39 3-3 pin assignments in 80-pin qfp for mc68hc912d60a . . . . . . 40 3-4 80-pin qfp mechanical dimensi ons (case no841b) . . . . . . . . 41 3-5 pll loop filter co nnections . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3-6 external oscillator connec tions . . . . . . . . . . . . . . . . . . . . . . . .45 5-1 mc68hc912d60a memory ma p . . . . . . . . . . . . . . . . . . . . . . . 83 6-1 access type vsbus control pins . . . . . . . . . . . . . . . . . . . . . . . 86 10-1 stop key wake-up filt er (falling edge trigger ) timing. . . . . . 135 11-1 internal clock relationships . . . . . . . . . . . . . . . . . . . . . . . . . . 139 11-2 pll functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 11-3 clock loss during normal operation . . . . . . . . . . . . . . . . . . . 144 11-4 no clock at power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 146 11-5 stop exit and fast stop recovery . . . . . . . . . . . . . . . . . . . 149 11-6 clock generation chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 11-7 clock chain for sci0, sc i1, rti, cop. . . . . . . . . . . . . . . . . . 164 11-8 clock chain for ect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 11-9 clock chain for ms can, spi, atd0, atd1 and bdm . . . . . . 166 12-1 mc68hc912d60a colpitts oscillator architecture. . . . . . . . . 177 12-2 mc68hc912d60c colpitts oscillator architecture. . . . . . . . . 180 12-3 mc68hc912d60c crystal with dc blocking capacitor . . . . . 192 12-4 mc68hc912d60p pierce oscillator ar chitecture. . . . . . . . . . 195 13-1 block diagram of pwm left-ali gned output channel . . . . . . 208 13-2 block diagram of pwm center-a ligned output channel . . . . 209 13-3 pwm clock sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 14-1 timer block diagram in latch mode. . . . . . . . . . . . . . . . . . . .225 14-2 timer block diagram in queue mode. . . . . . . . . . . . . . . . . . . 226
list of figures technical data mc68hc9 12d60a ? rev. 3.1 16 list of figures freescale semiconductor 14-3 8-bit pulse accumulators block dia gram . . . . . . . . . . . . . . . . 227 14-4 16-bit pulse accumulators block di agram . . . . . . . . . . . . . . . 228 14-5 block diagram for port7 with output compare / pulse accumulator a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 14-6 c3f-c0f interrupt flag setting . . . . . . . . . . . . . . . . . . . . . . .229 15-1 multiple serial interfac e block diagram . . . . . . . . . . . . . . . . . 264 15-2 serial communications interface block diagram . . . . . . . . . . 265 15-3 serial peripheral interface block dia gram . . . . . . . . . . . . . . . 277 15-4 spi clock format 0 (cpha = 0) . . . . . . . . . . . . . . . . . . . . . . . 278 15-5 spi clock format 1 (cpha = 1) . . . . . . . . . . . . . . . . . . . . . . . 279 15-6 normal mode and bidirecti onal mode. . . . . . . . . . . . . . . . . . . 280 16-1 mi bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290 16-2 biphase coding and error detection . . . . . . . . . . . . . . . . . . . . 292 16-3 mi bus block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 16-4 a typical mi bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 17-1 the can system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 17-2 user model for message buffer organi zation. . . . . . . . . . . . . 308 17-3 32-bit maskable identifier acceptance filters . . . . . . . . . . . . . 312 17-4 16-bit maskable acceptance filters . . . . . . . . . . . . . . . . . . . . 312 17-5 8-bit maskable acceptance filters . . . . . . . . . . . . . . . . . . . . . 313 17-6 sleep request / acknowle dge cycle . . . . . . . . . . . . . . . . . . 319 17-7 clocking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 17-8 segments within the bit time . . . . . . . . . . . . . . . . . . . . . . . . . 323 17-9 mscan12 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 17-10 message buffer organiza tion . . . . . . . . . . . . . . . . . . . . . . . . . 325 17-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 17-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 18-1 analog-to-digital converter block diagram . . . . . . . . . . . . . . 350 19-1 bdm host to target se rial bit timing. . . . . . . . . . . . . . . . . . . 381 19-2 bdm target to host se rial bit timing (logic 1) . . . . . . . . . . . 381 19-3 bdm target to host se rial bit timing (logic 0) . . . . . . . . . . . 382 20-1 timer inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 20-2 por and external reset timing diagr am . . . . . . . . . . . . . . . 415 20-3 stop recovery timing diagram . . . . . . . . . . . . . . . . . . . . . . 416 20-4 wait recovery timing diagram . . . . . . . . . . . . . . . . . . . . . . 417 20-5 interrupt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 20-6 port read timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .419 20-7 port write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .419
list of figures mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor list of figures 17 20-8 multiplexed expansion bus timing dia gram . . . . . . . . . . . . . 421 20-9 spi timing diagram (1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . 423 20-10 spi timing diagram (2 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . 424
list of figures technical data mc68hc9 12d60a ? rev. 3.1 18 list of figures freescale semiconductor
mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor list of tables 19 technical data ? mc68hc912d60a list of tables table title page 1-1 device ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1-2 development tools ordering information. . . . . . . . . . . . . . . . . 28 2-1 m68hc12 addressing mode summary . . . . . . . . . . . . . . . . . . 34 2-2 summary of indexed operat ions . . . . . . . . . . . . . . . . . . . . . . . 35 3-1 mc68hc912d60a power and ground connection summary . 44 3-2 mc68hc912d60a signal description summary . . . . . . . . . . . 50 3-3 mc68hc912d60a port description su mmary . . . . . . . . . . . . . 59 3-4 port pull-up, pull-down and redu ced drive summary . . . . . . 60 4-1 mc68hc912d60a register map . . . . . . . . . . . . . . . . . . . . . . . 62 5-1 mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5-2 mapping precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5-3 rfstr stretch bit definiti on . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5-4 exstr stretch bit definiti on . . . . . . . . . . . . . . . . . . . . . . . . . . 82 8-1 eediv selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 8-2 1k byte eeprom block protection . . . . . . . . . . . . . . . . . . . . 112 8-3 erase selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8-4 shadow word mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 9-1 interrupt vector map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 9-2 stacking order on entry to interrupts . . . . . . . . . . . . . . . . . . . 128 11-1 summary of stop mode exit conditions. . . . . . . . . . . . . . . . 155 11-2 summary of pseudo stop mode exit conditi ons . . . . . . . . . 155 11-3 clock monitor time-outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 11-4 real time interrupt rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 11-5 cop watchdog rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 13-1 clock a and clock b prescaler. . . . . . . . . . . . . . . . . . . . . . . . 212 13-2 pwm left-aligned boundar y conditions . . . . . . . . . . . . . . . . 222 13-3 pwm center-aligned bound ary conditions . . . . . . . . . . . . . . 222 14-1 compare result output action . . . . . . . . . . . . . . . . . . . . . . . . 238 14-2 edge detector circuit configuration . . . . . . . . . . . . . . . . . . . .238
list of tables technical data mc68hc9 12d60a ? rev. 3.1 20 list of tables freescale semiconductor 14-3 prescaler selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 15-1 baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 15-2 loop mode functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 15-3 ss output selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 15-4 spi clock rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 16-1 mi bus delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301 17-1 mscan12 interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . 315 17-2 mscan12 vscpu operating modes . . . . . . . . . . . . . . . . . . . .317 17-3 can standard compliant bit time segment settings . . . . . . 323 17-4 data length codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328 17-5 synchronization jump widt h . . . . . . . . . . . . . . . . . . . . . . . . . . 333 17-6 baud rate prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 17-7 time segment syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 17-8 time segment values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 17-9 identifier acceptance m ode settings . . . . . . . . . . . . . . . . . . . 341 17-10 identifier acceptance hit indication . . . . . . . . . . . . . . . . . . . . 342 18-1 result data formats available . . . . . . . . . . . . . . . . . . . . . . . . 361 18-2 left justified atd output codes . . . . . . . . . . . . . . . . . . . . . . 362 18-3 atd response to ba ckground debug enable . . . . . . . . . . . . 364 18-4 final sample time selection . . . . . . . . . . . . . . . . . . . . . . . . . 365 18-5 clock prescaler values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 18-6 conversion sequenc e length coding . . . . . . . . . . . . . . . . . . 367 18-7 result register assignm ent for different conversion sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 18-8 special channel conver sion select coding . . . . . . . . . . . . . . 368 18-9 analog input channel select coding . . . . . . . . . . . . . . . . . . . 369 18-10 multichannel mode resu lt register assignment (mult=1) . . 370 19-1 ipipe decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 19-2 hardware commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 19-3 bdm firmware commands . . . . . . . . . . . . . . . . . . . . . . . . . . 385 19-4 bdm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 19-5 ttago decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .392 19-6 ttago value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 19-7 instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 19-8 regn decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 19-9 breakpoint mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 19-10 breakpoint address rang e control . . . . . . . . . . . . . . . . . . . . 399 19-11 breakpoint read/write control . . . . . . . . . . . . . . . . . . . . . . . . 401
list of tables mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor list of tables 21 19-12 tag pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 20-1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .406 20-2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 20-3 dc electrical characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . 408 20-4 supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 20-5 atd dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . 409 20-6 analog converter characteristics (o perating) . . . . . . . . . . . . 410 20-7 atd ac characteristics (operating). . . . . . . . . . . . . . . . . . . .410 20-8 atd maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 20-9 eeprom characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 20-10 flash eeprom characteristics . . . . . . . . . . . . . . . . . . . . . . .412 20-11 pulse width modulator c haracteristics. . . . . . . . . . . . . . . . . . 412 20-12 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 20-13 peripheral port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .419 20-14 multiplexed expansion bu s timing. . . . . . . . . . . . . . . . . . . . . 420 20-15 spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 20-16 cgm characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 20-17 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 20-18 key wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .426 20-19 mscan12 wake-up time from sleep mode. . . . . . . . . . . . . . 426 21-1 suggested 8mhz synthes is pll filter elements (tracking mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 21-2 suggested 8mhz synthes is pll filter elements (acquisition mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
list of tables technical data mc68hc9 12d60a ? rev. 3.1 22 list of tables freescale semiconductor
mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor general description 23 technical data ? mc68hc912d60a section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.3 devices covered in this document. . . . . . . . . . . . . . . . . . . . . . 24 1.4 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.5 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.6 block diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.2 introduction the mc68hc912d60a microcontroller unit (mcu) is a 16-bit device available in two pack age options, 80-pin qfp and 112-pin tqfp. on- chip peripherals include a 16-bit central processing unit (cpu12), 60k bytes of flash eeprom, 2k bytes of ram, 1k bytes of eeprom, two asynchronous serial communication inte rfaces (sci), a serial peripheral interface (spi), an enhanced captur e timer (ect), two (one on 80qfp) 8-channel,10-bit analog-to-digital converters (atd), a four-channel pulse-width modulator (p wm), and a can 2.0 a, b software compatible module (mscan12). system resour ce mapping, clo ck generation, interrupt control and bus interfaci ng are managed by the lite integration module (lim). the mc 68hc912d60a has fu ll 16-bit data paths throughout, however, the external bus can operat e in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. the inclusion of a pll circuit allows power consumption and performance to be adjusted to suit operational re quirements. in addition to the i/o ports available in each module, 16 (2 on 80qfp) i/o port pins are available with key-wa ke-up capability from stop or wait mode.
general description technical data mc68hc9 12d60a ? rev. 3.1 24 general description freescale semiconductor 1.3 devices covered in this document the mc68hc912d60c and mc68hc912d60p are devices similar to the mc68hc912d60a, but with different oscillator configurations. refer to section 12. oscillator for more details. the generic term mc68hc 912d60a is used throug hout this document to mean all derivatives m entioned above, except in section 12. oscillator , where it refers only to the mc68hc912d60a device. 1.4 features 16-bit cpu12 ? upward compatible with m68hc11 instruction set ? interrupt stacking and progra mmer?s model identical to m68hc11 ? 20-bit alu ? instruction queue ? enhanced indexed addressing multiplexed bus ? single chip or expanded ? 16 address/16 data wide or 16 address/8 data narrow mode two 8-bit ports with key wake- up interrupt (2 pins only are available on 80qfp) and one i 2 c start bit detector (112tqfp only) memory ? 60k byte flash eeprom, made of a 28k m odule and a 32k module with 8k bytes protected boot section in each module (mc68hc912d60a) ? 1k byte eeprom ?2k byte ram
general description features mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor general description 25 analog-to-digital converters ? 2 x 8-channels, 10-bit resolution in 112tqfp ? 1 x 8-channels, 8-bit resolution in 80qfp 1m bit per second, can 2.0 a, b software compatible module ? two receive and three transmit buffers ? flexible identifier filter program mable as 2 x 32 bit, 4 x 16 bit or 8x8bit ? four separate interrupt channel s for rx, tx, error and wake-up ? low-pass filter wake-up function ? in 80qfp, only txcan and rx can pins are available ? loop-back for self test operation ? programmable link to a timer input capture channel, for time- stamping and network synchronization. enhanced capture timer (ect) ? 16-bit main counter with 7-bit prescaler ? 8 programmable input capture or output compare channels; 4 of the 8 input captures with buffer ? input capture filter s and buffers, three successive captures on four channels, or two captur es on four channels with a capture/compare selectab le on the remaining four ? four 8-bit or two 16- bit pulse accumulators ? 16-bit modulus down-counter with 4-bit prescaler ? four user-selectable delay counters for si gnal filtering 4 pwm channels with program mable period and duty cycle ? 8-bit 4-channel or 16-bit 2-channel ? separate control for each pulse width and duty cycle ? center- or left-aligned outputs ? programmable clock select logic with a wide range of frequencies
general description technical data mc68hc9 12d60a ? rev. 3.1 26 general description freescale semiconductor serial interfaces ? two asynchronous serial comm unications interfaces (sci) ? mi-bus implemented on final devices ? synchronous serial perip heral interface (spi) lim (light integration module) ? wcr (windowed cop wa tchdog, real time interrupt, clock monitor) ? roc (reset and clocks) ? mebi (multiplexed external bus interface) ? mbi (internal bus interface and map) ? int (interrupt control) clock generation ? phase-locked loop cl ock frequency multiplier ? limp home mode in absence of external clock ? slow mode divider ? low power 0.5 to 16 mhz crystal oscillator reference clock ? option of a pierce or colpitts oscillator 112-pin tqfp package or 80-pin qfp package ? up to 68 general-purpose i/o lines, plus up to 18 input-only lines in 112tqfp or up to 48 general-purpose i/o lines, plus up to 10 input-only lines in 80qfp 8mhz operation at 5v development support ? single-wire backgr ound debug? mode (bdm) ? on-chip hardware breakpoints
general description ordering information mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor general description 27 1.5 ordering information * important: m temperature operatio n is available only for single chip modes table 1-1. device ordering information package ambient temperature order number range designator 112-pin tqfp single tray 60 pcs ?40 to +85 c c mc912d60acpv8 ?40 to +105 c v mc912d60avpv8 ?40 to +125 c m* mc912d60ampv8 80-pin tqfp single tray 84 pcs ?40 to +85 c c mc912d60acfu8 ?40 to +105 c v mc912d60avfu8 ?40 to +125 c m* mc912d60amfu8 112-pin tqfp single tray 60 pcs ?40 to +85 c c mc912d60ccpv8 ?40 to +105 c v mc912d60cvpv8 ?40 to +125 c m* mc912d60cmpv8 80-pin tqfp single tray 84 pcs ?40 to +85 c c mc912d60ccfu8 ?40 to +105 c v mc912d60cvfu8 ?40 to +125 c m* mc912d60cmfu8 112-pin tqfp single tray 60 pcs ?40 to +85 c c mc912d60pcpv8 ?40 to +105 c v mc912d60pvpv8 ?40 to +125 c m* mc912d60pmpv8 80-pin tqfp single tray 84 pcs ?40 to +85 c c mc912d60pcfu8 ?40 to +105 c v MC912D60PVFU8 ?40 to +125 c m* mc912d60pmfu8
general description technical data mc68hc9 12d60a ? rev. 3.1 28 general description freescale semiconductor note: sdbug12 is a p & e micro product. it can be obta ined from p & e from their web site (http: //www.pemicro.com) fo r approximately $100. third party tools: http ://www.mcu.motsps.com/ dev_tools/3rd/index.html table 1-2. development t ools ordering information description name order number mcuez free from world wide web serial debug interface sdi m68sdil (3?5v), m68dil12 (sdil + mcuez + sdbug12) evaluation board evb m68evb912d60 (evb only) m68kit912d60 (evb + sdil12)
general description block diagrams mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor general description 29 1.6 block diagrams figure 1-1 . mc68hc912d60a 112-pin qfp block diagram txcan ddrg portg kwg4 kwg3 kwg2 kwg1 kwg0 pg7 kwg6 kwg5 pg4 pg3 pg2 pg1 pg0 pg7 pg6 pg5 ddrh porth ph4 ph3 ph2 ph1 ph0 ph7 ph6 ph5 kwh4 kwh3 kwh2 kwh1 kwh0 kwh7 kwh6 kwh5 pgupd phupd pgupd phupd ioc0 ioc1 ioc2 ioc3 ioc4 ioc5 ioc6 ioc7 ddrt port t 60k byte flash eeprom 2k byte ram port e enhanced pt0 pt1 pt2 pt3 pt4 pt5 pt6 pt7 spi ddrs port s port ad1 pe1 pe2 pe4 pe5 pe6 pe3 pad13 pad14 pad15 pad16 pad17 vddad vssad vrh1 vrl1 pad10 pad11 pad12 reset extal xtal pw0 pw1 pw2 pw3 pwm ddrp port p pp0 pp1 pp2 pp3 vdd 2 vss 2 sci0 (mi bus) rxd0 txd0 rxd1 txd1 siso/miso momi/mosi sck ss ps0 ps1 ps2 ps3 ps4 ps5 ps6 ps7 1k byte eeprom pe0 pe7 an13 an14 an15 an16 an17 vddad vssad vrh1 vrl1 an10 an11 an12 bkgd eclk r/w lstrb /taglo moda/ipipe0 modb/ipipe1/cgmtst xirq dbe/ cal/eclk capture timer lite irq pcan7 pcan6 pcan5 pcan4 sci1 integration module (lim) cpu12 periodic interrupt cop watchdog clock monitor single-wire background debug module breakpoints pll vsspll xfc vddpll can rxcan ddra port a ddrb port b pa 4 pa 3 pa 2 pa 1 pa 0 pa 7 pa 6 pa 5 pb4 pb3 pb2 pb1 pb0 pb7 pb6 pb5 data15 multiplexed address/data bus a d d r 1 5 a d d r 1 4 a d d r 1 3 a d d r 1 2 a d d r 1 1 a d d r 1 0 a d d r 9 a d d r 8 data14 data13 data12 data11 data10 data9 data8 a d d r 7 a d d r 6 a d d r 5 a d d r 4 a d d r 3 a d d r 2 a d d r 1 a d d r 0 data7 data6 data5 data4 data3 data2 data1 data0 atd1 port ad0 pad03 pad04 pad05 pad06 pad07 vrh0 vrl0 pad00 pad01 pad02 an03 an04 an05 an06 an07 vddad vssad vrh0 vrl0 an00 an01 an02 atd0 i/o data7 data6 data5 data4 data3 data2 data1 data0 wide bus narrow bus pcan1 pcan0 vddx 2 vssx 2 power for internal circuitry power for i/o drivers i/o pp4 pp5 pp6 pp7 pcan3 pcan2
general description technical data mc68hc9 12d60a ? rev. 3.1 30 general description freescale semiconductor figure 1-2 . mc68hc912d60a 80-pi n qfp block diagram pt0 pt1 pt2 pt3 pt4 pt5 pt6 pt7 txcan ddrg portg kwg4 kwg3 kwg2 kwg1 kwg0 pg7 kwg6 kwg5 pg4 ddrh porth ph4 kwh4 kwh3 kwh2 kwh1 kwh0 kwh7 kwh6 kwh5 pgupd(vdd) phupd(vss) ioc0 ioc1 ioc2 ioc3 ioc4 ioc5 ioc6 ioc7 ddrt port t 60k byte flash eeprom 2k byte ram port e enhanced spi ddrs port s pe1 pe2 pe4 pe5 pe6 pe3 vddad vssad reset extal xtal pw0 pw1 pw2 pw3 pwm ddrp port p pp0 pp1 pp2 pp3 vdd 2 vss 2 sci0 (mi bus) rxd0 txd0 rxd1 txd1 siso/miso momi/mosi sck ss ps0 ps1 ps2 ps3 ps4 ps5 ps6 ps7 1k byte eeprom pe0 pe7 bkgd capture timer sci1 cpu12 periodic interrupt cop watchdog clock monitor single-wire background debug module breakpoints pll vsspll xfc vddpll can rxcan ddra port a ddrb port b pa 4 pa 3 pa 2 pa 1 pa 0 pa 7 pa 6 pa 5 pb4 pb3 pb2 pb1 pb0 pb7 pb6 pb5 data15 multiplexed address/data bus a d d r 1 5 a d d r 1 4 a d d r 1 3 a d d r 1 2 a d d r 1 1 a d d r 1 0 a d d r 9 a d d r 8 data14 data13 data12 data11 data10 data9 data8 a d d r 7 a d d r 6 a d d r 5 a d d r 4 a d d r 3 a d d r 2 a d d r 1 a d d r 0 data7 data6 data5 data4 data3 data2 data1 data0 port ad0 pad03 pad04 pad05 pad06 pad07 vrh0 vrl0 pad00 pad01 pad02 an03 an04 an05 an06 an07 vddad vssad vrh0 vrl0 an00 an01 an02 atd0 i/o data7 data6 data5 data4 data3 data2 data1 data0 wide bus narrow bus pcan1 pcan0 vddx 2 vssx 2 power for internal circuitry power for i/o drivers pp4 pp5 pp6 pp7 ddrcan port can pcan7 pcan6 pcan5 pcan4 pcan3 pcan2 eclk r/w lstrb /taglo moda/ipipe0 modb/ipipe1/cgmtst xirq dbe/ cal/eclk lite irq integration module (lim) port ad1 an13 an14 an15 an16 an17 vddad vssad vrh1 vrl1 an10 an11 an12 atd1 several i/o on ports g, h and can are unavailable externally on the 80-pin qfp package. these in- ternal pins should either be defined as outputs or have their pull-ups/downs enabled. note:
mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor central processing unit 31 technical data ? mc68hc912d60a section 2. central processing unit 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.3 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.4 data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.5 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.6 indexed addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.7 opcodes and operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.2 introduction the cpu12 is a high-speed, 16 -bit processing unit. it has full 16-bit data paths and wider internal registers ( up to 20 bits) for high-speed extended math instructions. the instruction set is a proper superset of the m68hc11instruction set. the cpu12 al lows instructions with odd byte counts, including many single-byte in structions. this provides efficient use of rom space. an instruction queue buffers program information so the cpu always has immediate access to at leas t three bytes of machine code at the start of every instruction. the cpu12 also offers an extensive set of indexed addressing capabilities. 2.3 programming model cpu12 registers are an integral pa rt of the cpu and are not addressed as if they were memory locations.
central processing unit technical data mc68hc9 12d60a ? rev. 3.1 32 central processing unit freescale semiconductor figure 2-1. programming model accumulators a and b are general-purpose 8-bit accumulators used to hold operands and resu lts of arithmetic ca lculations or data manipulations. some instructions tr eat the combinati on of these two 8- bit accumulators as a 16-bit doubl e accumulator (accumulator d). index registers x and y are used for index ed addressing m ode. in the indexed addressing mode, the contents of a 16-bit index register are added to 5-bit, 9-bit, or 16-bit constants or the content of an accumulator to form the effective addre ss of the operand to be us ed in the instruction. stack pointer (sp) points to t he last stack locati on used. the cpu12 supports an automatic pr ogram stack that is used to save system context during subr outine calls and interrupts, and can also be used for temporary storage of dat a. the stack pointer c an also be used in all indexed addressing modes. program counter is a 16-bit register that holds the address of the next instruction to be executed. the pr ogram counter can be used in all indexed addressing modes exce pt autoincrement/decrement. 7 15 15 15 15 15 d ix iy sp pc ab n sxh i zvc 0 0 0 0 0 0 7 0 condition code register 8-bit accumulators a & b 16-bit double accumulator d index register x index register y stack pointer program counter or
central processing unit data types mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor central processing unit 33 condition code register (ccr) contains five status indicators, two interrupt masking bits, and a stop disable bit. th e five flags are half carry (h), negative (n), zero (z), overflow (v), and carry/borrow (c). the half-carry flag is used only for bcd arithmetic operations. the n, z, v, and c status bits allow for branching based on the results of a previous operation. after a reset, the cpu fetches a ve ctor from the ap propriate address and begins executing instructions. the x and i interrupt mask bits are set to mask any interrupt reques ts. the s bit is also se t to inhibit the stop instruction. 2.4 data types the cpu12 supports the following data types: bit data 8-bit and 16-bit si gned and unsi gned integers 16-bit unsigned fractions 16-bit addresses a byte is eight bits wide and can be accessed at any byte location. a word is composed of two consecutiv e bytes with the most significant byte at the lower value address. there are no special requirements for alignment of instructions or operands. 2.5 addressing modes addressing modes determine how t he cpu accesses me mory locations to be operated upon. the cpu12 includes all of the addressing modes of the m68hc11 cpu as well as several new forms of indexed addressing. table 2-1 is a summary of the available addressing modes.
central processing unit technical data mc68hc9 12d60a ? rev. 3.1 34 central processing unit freescale semiconductor table 2-1. m68hc12 addressing mode summary addressing mode source format abbreviation description inherent inst (no externally supplied operands) inh operands (if any) are in cpu registers immediate inst # opr8i or inst # opr16i imm operand is included in instruction stream 8- or 16-bit size implied by context direct inst opr8a dir operand is the lower 8-bits of an address in the range $0000 ? $00ff extended inst opr16a ext operand is a 16-bit address relative inst rel8 or inst rel16 rel an 8-bit or 16-bit relative offset from the current pc is supplied in the instruction indexed (5-bit offset) inst oprx5 , xysp idx 5-bit signed constant offset from x, y, sp, or pc indexed (auto pre-decrement) inst oprx3 , ? xys idx auto pre-decrement x, y, or sp by 1 ~ 8 indexed (auto pre-increment) inst oprx3 ,+ xys idx auto pre-increment x, y, or sp by 1 ~ 8 indexed (auto post-decrement) inst oprx3 , xys ? idx auto post-decrement x, y, or sp by 1 ~ 8 indexed (auto post-increment) inst oprx3 , xys + idx auto post-increment x, y, or sp by 1 ~ 8 indexed (accumulator offset) inst abd , xysp idx indexed with 8-bit (a or b) or 16-bit (d) accumulator offset from x, y, sp, or pc indexed (9-bit offset) inst oprx9 , xysp idx1 9-bit signed constant offset from x, y, sp, or pc (lower 8-bits of offset in one extension byte) indexed (16-bit offset) inst oprx16 , xysp idx2 16-bit constant offset from x, y, sp, or pc (16-bit offset in two extension bytes) indexed-indirect (16-bit offset) inst [ oprx16 , xysp ] [idx2] pointer to operand is found at... 16-bit constant offset from x, y, sp, or pc (16-bit offset in two extension bytes) indexed-indirect (d accumulator offset) inst [d, xysp ] [d,idx] pointer to operand is found at... x, y, sp, or pc plus the value in d
central processing unit indexed addressing modes mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor central processing unit 35 2.6 indexed addressing modes the cpu12 indexed modes reduce ex ecution time and eliminate code size penalties for usi ng the y index register . cpu12 indexed addressing uses a postbyte plus zero, one, or two extension bytes after the instruction opcode. the postbyte and extensions do the following tasks: specify which index register is used. determine whether a value in an a ccumulator is used as an offset. enable automatic pre- or post-increment or decrement specify use of 5-bit, 9-bi t, or 16-bit si gned offsets. table 2-2. summary of indexed operations postbyte code (xb) source code syntax comments rr0nnnnn ,r n,r ?n,r 5-bit constant offset n = ?16 to +15 rr can specify x, y, sp, or pc 111rr0zs n,r ?n,r constant offset (9- or 16-bit signed) z-0 = 9-bit with sign in lsb of postbyte(s) 1 = 16-bit if z = s = 1, 16-bit offset indexed-indirect (see below) rr can specify x, y, sp, or pc 111rr011 [n,r] 16-bit offset indexed-indirect rr can specify x, y, sp, or pc rr1pnnnn n,?r n,+r n,r? n,r+ auto pre-decrement/increment or auto post- decrement/increment ; p = pre-(0) or post-(1), n = ?8 to ?1, +1 to +8 rr can specify x, y, or sp (pc not a valid choice) 111rr1aa a,r b,r d,r accumulator offset (unsigned 8-bit or 16-bit) aa-00 = a 01 = b 10 = d (16-bit) 11 = see accumulator d offset indexed-indirect rr can specify x, y, sp, or pc 111rr111 [d,r] accumulator d offset indexed-indirect rr can specify x, y, sp, or pc
central processing unit technical data mc68hc9 12d60a ? rev. 3.1 36 central processing unit freescale semiconductor 2.7 opcodes and operands the cpu12 uses 8-bit opcodes. each opcode id entifies a particular instruction and associ ated addressing mode to the cpu. several opcodes are require d to provide each instru ction with a range of addressing capabilities. only 256 opcodes would be available if the range of values were restricted to the number that ca n be represented by 8-bit binary numbers. to expand the number of opcodes, a se cond page is added to the opcode map. opc odes on the second p age are preceded by an additional byte with the value $18. to provide additional addressing fl exibility, opcodes can also be followed by a postbyte or extension bytes. post bytes implement certain forms of indexed addre ssing, transfers, exchan ges, and loop primitives. extension bytes contain additional program information such as addresses, offsets, and immediate data.
mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor pinout and signal descriptions 37 technical data ? mc68hc912d60a section 3. pinout and signal descriptions 3.1 contents 3.2 mc68hc912d60a pin assignments in 112-pin qfp . . . . . . . . 38 3.3 mc68hc912d60a pin assignments in 80-pin qfp . . . . . . . . . 40 3.4 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.5 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.6 port signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
pinout and signal descriptions technical data mc68hc9 12d60a ? rev. 3.1 38 pinout and signal descriptions freescale semiconductor 3.2 mc68hc912d60a pin assignments in 112-pin qfp figure 3-1. pin assignments in 112-pin tqfp for mc68hc912d60a pp3/pw3 pp4 pp5 pp6 pp7 v ddx v ssx pcan0/rxcan pcan1/txcan pcan2 pcan3 pcan4 pcan5 pcan6 pcan7 test ps7/ss ps6/sck ps5/sdo/mosi ps4/sdi/miso ps3/txd1 ps2/rxd1 ps1/txd0 ps0/rxd0 v ssa v rl1 v rh1 v dda mc68hc912d60a 112tqfp pad17/an17 pad07/an07 pad16/an16 pad06/an06 pad15/an15 pad05/an05 pad14/an14 pad04/an04 pad13/an13 pad03/an03 pad12/an12 pad02/an02 pad11/an11 pad01/an01 pad10/an10 pad00/an00 v rl0 v rh0 v ss v dd pa7/addr15/data15/data7 pa6/addr14/data14/data6 pa5/addr13/data13/data5 pa4/addr12/data12/data4 pa3/addr11/data11/data3 pa2/addr10/data10/data2 pa1/addr9/data9/data1 pa0/addr8/data8/data0 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 addr6/data6/pb6 addr7/data7/pb7 kwh7/ph7 kwh6/ph6 kwh5/ph5 kwh4/ph4 eclk /dbe /cal/pe7 cgmtst/modb/ipipe1/pe6 moda/ipipe0/pe5 eclk/pe4 v ssx phupd v ddx v ddpll xfc v sspll reset extal xtal kwh3/ph3 kwh2/ph2 kwh1/ph1 kwh0/ph0 lstrb /taglo /pe3 r/w /pe2 irq /pe1 xirq /pe0 pw2/pp2 pw1/pp1 pw0/pp0 ioc0/pt0 ioc1/pt1 ioc2/pt2 ioc3/pt3 pg7 kwg6/pg6 kwg5/pg5 kwg4/pg4 v dd pgupd v ss ioc4/pt4 ioc5/pt5 ioc6/pt6 ioc7/pt7 kwg3/pg3 kwg2/pg2 kwg1/pg1 kwg0/pg0 smodn/taghi /bkgd addr0/data0/pb0 addr1/data1/pb1 addr2/data2/pb2 addr3/data3/pb3 addr4/data4/pb4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 addr5/data5/pb5 note: test = this pin is used for factory test purposes. it is recommended that this pin is not connected in the application, but it may be bonded to 5.5 v max without issue. never apply voltage higher than 5.5 v to this pin.
pinout and signal descriptions mc68hc912d60a pin assignments in 112-pin qfp mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor pinout and signal descriptions 39 figure 3-2. 112-pin tqfp mechanical dim ensions ( case no. 987) dim a min max 20.000 bsc millimeters a1 10.000 bsc b 20.000 bsc b1 10.000 bsc c --- 1.600 c1 0.050 0.150 c2 1.350 1.450 d 0.270 0.370 e 0.450 0.750 f 0.270 0.330 g 0.650 bsc j 0.090 0.170 k 0.500 ref p 0.325 bsc r1 0.100 0.200 r2 0.100 0.200 s 22.000 bsc s1 11.000 bsc v 22.000 bsc v1 11.000 bsc y 0.250 ref z 1.000 ref aa 0.090 0.160 11 11 13 7 13 view y l-m 0.20 n t 4x 4x 28 tips pin 1 ident 1 112 85 84 28 57 29 56 b v v1 b1 a1 s1 a s view ab 0.10 3 c c2 2 0.050 seating plane gage plane 1 view ab c1 (z) (y) e (k) r2 r1 0.25 j1 view y j1 p g 108x 4x section j1-j1 base rotated 90 counterclockwise metal j aa f d l-m m 0.13 n t 1 2 3 c l l-m 0.20 n t l n m t t 112x x x=l, m or n r r 8 3 0 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. datums l, m and n to be determined at seating plane, datum t. 4. dimensions s and v to be determined at seating plane, datum t. 5. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b include mold mismatch. 6. dimension d does not include dambar protrusion. allowable dambar protrusion shall not cause the d dimension to exceed 0.46.
pinout and signal descriptions technical data mc68hc9 12d60a ? rev. 3.1 40 pinout and signal descriptions freescale semiconductor 3.3 mc68hc912d60a pin assignments in 80-pin qfp figure 3-3. pin assignments in 80-pin qfp for mc68hc912d60a 60 59 57 56 55 54 53 52 51 50 49 48 47 46 45 58 1 2 4 5 6 7 8 9 10 11 12 13 14 15 16 3 44 43 42 41 18 20 19 17 80 79 77 76 75 74 73 72 71 70 69 68 67 66 65 78 64 63 62 61 21 22 24 25 26 27 28 29 30 31 32 33 34 35 36 23 38 40 39 37 mc68hc912d60a 80 qfp pp3/pw3 pp4 pp5 pp6 pp7 v ddx v ssx pcan0/rxcan pcan1/txcan test ps7/ss ps6/sck ps5/sdo/mosi ps4/sdi/miso ps3/txd1 ps2/rxd1 ps1/txd0 ps0/rxd0 v ssad v ddad pad07/an07 pad06/an06 pad05/an05 pad04/an04 pad03/an03 pad02/an02 pad01/an01 pad00/an00 v rl0 v rh0 v ss v dd pa7/addr15/data15/data7 pa6/addr14/data14/data6 pa5/addr13/data13/data5 pa4/addr12/data12/data4 pa3/addr11/data11/data3 pa2/addr10/data10/data2 pa1/addr9/data9/data1 pa0/addr8/data8/data0 addr5/data5/pb5 addr6/data6/pb6 addr7/data7/pb7 kwh4/ph4 eclk /dbe /cal/pe7 cgmtst/modb/ipipe1/pe6 moda/ipipe0/pe5 eclk/pe4 v ssx v ddx v ddpll xfc v sspll reset extal xtal lstrb /taglo /pe3 r/w /pe2 irq /pe1 xirq /pe0 pw2/pp2 pw1/pp1 pw0/pp0 ioc0/pt0 ioc1/pt1 ioc2/pt2 ioc3/pt3 kwg4/pg4 v dd v ss ioc4/pt4 ioc5/pt5 ioc6/pt6 ioc7/pt7 smodn/taghi/ bkgd addr0/data0/pb0 addr1/data1/pb1 addr2/data2/pb2 addr3/data3/pb3 addr4/data4/pb4 note: test = this pin is used for factory test purposes. it is recommended that this pin is not connected in the application, but it may be bonded to 5.5 v max without issue. never apply voltage higher than 5.5 v to this pin.
pinout and signal descriptions mc68hc912d60a pin assignments in 80-pin qfp mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor pinout and signal descriptions 41 figure 3-4. 80-pin qf p mechanical dimensio ns (case no. 841b) notes: 1. dimensioning a nd tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane -h- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums -a-, -b- and -d- to be determined at datum plane -h-. 5. dimensions s and v to be determined at seating plane -c-. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b do include mold mismatch and are determined at datum plane -h-. 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 total in section b-b 61 60 detail a l 41 40 80 -a- l -d- a s a-b m 0.20 d s h 0.05 a-b s 120 21 -b- b v j f n d view rotated 90 detail a b b p -a-,-b-,-d- e h g m m detail c seating plane -c- c datum plane 0.10 -h- datum plane -h- u t r q k w x detail c dim min max millimeters a 13.90 14.10 b 13.90 14.10 c 2.15 2.45 d 0.22 0.38 e 2.00 2.40 f 0.22 0.33 g 0.65 bsc h --- 0.25 j 0.13 0.23 k 0.65 0.95 l 12.35 ref m 5 10 n 0.13 0.17 p 0.325 bsc q 0 7 r 0.13 0.30 s 16.95 17.45 t 0.13 --- u 0 --- v 16.95 17.45 w 0.35 0.45 x 1.6 ref s a-b m 0.20 d s c s a-b m 0.20 d s h 0.05 d s a-b m 0.20 d s c s a-b m 0.20 d s c
pinout and signal descriptions technical data mc68hc9 12d60a ? rev. 3.1 42 pinout and signal descriptions freescale semiconductor 3.4 power supply pins mc68hc912d60a power a nd ground pins are described below and summarized in table 3-1 . all power supply pins must be connected to appropriate supplies. on no account must any pins be left floating. 3.4.1 internal power (v dd ) and ground (v ss ) power is supplied to the mcu through v dd and v ss . because fast signal transitions place high, short-dur ation current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the mcu as possible. bypass requirements depend on how heavily t he mcu pins are loaded. 3.4.2 external power (v ddx ) and ground (v ssx ) external power and ground for i/o drivers. because fast signal transitions place high, short-dur ation current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the mcu as possible. bypass requirements depend on how heavily t he mcu pins are loaded. 3.4.3 v dda , v ssa provides operating voltage and gr ound for the anal og-to-digital converter. this allows the supply vo ltage to the atd to be bypassed independently. connecting v dda to v dd if the atd modules are not used will not result in an in crease of power consumption. 3.4.4 analog to digita l reference voltages (v rh , v rl ) v rh0 , v rl0 : reference voltage high and low for atd converter 0. v rh1 , v rl1 : reference voltage high and low for atd converter 1. if the atd modules ar e not used, leaving v rh connected to v dd will not result in an increase of power consumption.
pinout and signal descriptions power supply pins mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor pinout and signal descriptions 43 3.4.5 v ddpll , v sspll provides operating voltage and gr ound for the phased-locked loop. this allows the supply voltage to the pll to be bypassed independently. note: the vsspll pin should always be grounded even if the pll is not used. the vddpll pin should not be left floating. it is recommended to connect the vddpll pin to grou nd if the pll is not used. 3.4.6 xfc pll loop filter. please see appendix: cgm practical aspects for information on how to calculate pll loop filter elements. any current leakage on this pi n must be avoided. figure 3-5. pll lo op filter connections if vddpll is connected to vss (this is normal case), then the xfc pin should either be left floati ng or connected to vss ( never to vdd). if vddpll is tied to vdd but the pll is switched off (pllon bit cleared), then the xfc pin should be connect ed preferably to vddpll (i.e. ready for vco mini mum frequency). mcu xfc r 0 c 0 c a vddpll
pinout and signal descriptions technical data mc68hc9 12d60a ? rev. 3.1 44 pinout and signal descriptions freescale semiconductor 3.5 signal descriptions 3.5.1 crystal driver and exter nal clock input (xtal, extal) these pins provide the interface fo r either a cryst al or a cmos compatible clock to control the inter nal clock generator ci rcuitry. out of reset the frequency applied to extal is twice the desired e?clock rate. all the device clocks are derived from the extal input frequency. 3.5.1.1 crystal connections refer to section 12. oscillator for details of cr ystal connections. table 3-1. mc68hc912d60a powe r and ground connection summary mnemonic pin number description 80-pin qfp 112-pin qfp v dd 9, 49 12, 65 internal power and ground. v ss 10, 50 14, 66 v ddx 30, 75 42, 107 external power and ground, supply to pin drivers. v ssx 29, 74 40, 106 v dda 61 85 operating voltage and ground for the analog-to-digital converter, allows the supply voltage to the a/d to be bypassed independently. v ssa 62 88 v rh1 ?86 reference voltages for the analog-to-digital converter 1 v rl1 ?87 v rh0 51 67 reference voltages for the analog-to-digital converter 0. v rl0 52 68 v ddpll 31 43 provides operating voltage and ground for the phased-locked loop. this allows the supply voltage to the pll to be bypassed independently. v sspll 33 45
pinout and signal descriptions signal descriptions mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor pinout and signal descriptions 45 note: when selecting a crystal, it is re commended to use one wi th the lowest possible frequency in order to minimise emc emissions. 3.5.1.2 external os cillator connections xtal is the crystal output . the xtal pin must be left unterminated when an external cmos compatible clo ck input is connected to the extal pin. the xtal output is normally in tended to drive only a crystal. the xtal output can be buffered with a high-impedance buf fer to drive the extal input of another device. figure 3-6. external oscillator connections 3.5.2 e-clock output (eclk) eclk is the output conn ection for the internal bus clock and is used to demultiplex the address and data and is used as a timing reference. eclk frequency is equal to 1/2 the crystal frequency out of reset. the eclk output is turned off in single chip user m ode to reduce the effects of rfi. it can be turn ed on if necessary. in singl e-chip special mode, the eclk is turned on at reset and can be turned off. in special peripheral mode the eclk is an i nput to the mcu. all clocks, including the eclk, are halted when the mcu is in stop mode. it is possible to configure the mcu to interface to slow external memory . eclk can be stretched for such accesses. 3.5.3 reset (reset ) an active low bidirect ional contro l signal, reset , acts as an input to initialize the mcu to a known start-up state. it also acts as an open-drain nc mcu extal xtal 2 x e cmos-compatible external oscillator
pinout and signal descriptions technical data mc68hc9 12d60a ? rev. 3.1 46 pinout and signal descriptions freescale semiconductor output to indicate that an internal fa ilure has been detecte d in either the clock monitor or cop watchdog ci rcuit. the mcu goes into reset asynchronously and comes out of re set synchronously. this allows the part to reach a pr oper reset state even if the clocks have failed, while allowing synchroniz ed operation when starting out of reset. it is important to use an external low-voltage reset circuit (such as mc34064 or mc34164) to prevent corruption of ram or eeprom due to power transitions. the reset sequence is initiated by any of the following events: power-on-reset (por) cop watchdog enabled and watchdog timer times out clock monitor enabled an d clock monitor detec ts slow or stopped clock user applies a low le vel to the reset pin external circuitry connected to the reset pin should not include a large capacitance that would interf ere with the abili ty of this signal to rise to a valid logic one within nine bus cycles after the low drive is released. upon detection of any rese t, an internal circuit drives the reset pin low and a clocked reset sequence controls when the mcu ca n begin normal processing. in the case of por or a clock monitor error, a 4096 cycle oscillator startup delay is impos ed before the reset recovery sequence starts (reset is driven low throughou t this 4096 cycle delay ). the internal reset recovery sequence then drives reset low for 16 to 17 cycles and releases the drive to allow reset to rise. nine cycles later this circuit samples the reset pin to see if it has risen to a logic one level. if reset is low at this point, the reset is a ssumed to be coming from an external request and the internally latched states of the cop timeout and clock monitor failure are cleared so the normal rese t vector ($fffe:ffff) is taken when reset is finally released. if reset is high after this nine cycle delay, the reset source is tentativel y assumed to be either a cop failure or a clock monitor fail. if the internal ly latched state of the clock monitor fail circuit is true, proc essing begins by fetching th e clock monitor vector ($fffc:fffd). if no clock monitor failure is indi cated, and the latched state of the cop timeout is true, pr ocessing begins by fetching the cop
pinout and signal descriptions signal descriptions mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor pinout and signal descriptions 47 vector ($fffa:fffb). if neither clock monitor fail nor cop timeout are pending, processing begins by fe tching the normal reset vector ($fffe:ffff). 3.5.4 maskable in terrupt request (irq ) the irq input provides a means of ap plying asynchronous interrupt requests to the mcu. ei ther falling edge- sensitive triggering or level- sensitive triggering is program selectable (intcr register). irq is always enabled and configured to level- sensitive triggeri ng at reset. it can be disabled by clearing the irqe n bit (intcr regi ster). when the mcu is reset the irq function is masked in t he condition code register. this pin is always an input and can always be read . there is an active pull-up on this pin while in reset and immediatel y out of reset. the pull- up can be turned off by cleari ng pupe in the pucr register. 3.5.5 nonmaskable interrupt (xirq ) the xirq input provides a means of requesting a nonmask able interrupt after reset initialization. during re set, the x bit in the condition code register (ccr) is set and any interrupt is masked until mcu software enables it. because the xirq input is level sensit ive, it can be connected to a multiple-source wired-or network. this pi n is always an input and can always be read. there is an active pull-up on this pin while in reset and immediately out of reset. the pul l-up can be turned off by clearing pupe in the pucr register. xirq is often used as a power loss detect interrupt. whenever xirq or irq are used with multiple interrupt sources (irq must be configured for level-sensitive operation if there is more than one source of irq interrupt), each source must drive the interrupt input with an open-drain type of driver to avoi d contention between outputs. there must also be an interlo ck mechanism at each interr upt source so that the source holds the interrupt line low until the mc u recognizes and acknowledges the interrupt request. if the interrupt line is held low, the mcu will recognize another interrupt as soon as t he interrupt mask bit in the mcu is cleared ( normally upon return from an interrupt).
pinout and signal descriptions technical data mc68hc9 12d60a ? rev. 3.1 48 pinout and signal descriptions freescale semiconductor 3.5.6 mode select (s modn, moda, and modb) the state of these pins during rese t determine the mcu operating mode. after reset, moda and mo db can be configured as instruction queue tracking signals ipipe0 and ipipe1 . moda and modb ha ve active pull- downs during reset. the smodn pin has an active pull-up w hen configured as input. this pin can be used as bkgd or taghi after reset. 3.5.7 single-wire b ackground mode pin (bkgd) the bkgd pin receives and trans mits serial background debugging commands. a special self-timing protoc ol is used. the bkgd pin has an active pull-up when configured as in put; bkgd has no pull-up control. refer to development support . 3.5.8 external addres s and data buses (ad dr[15:0] and data[15:0]) external bus pins share function wit h general-purpose i/o ports a and b. in single-chip operating modes, the pins can be used for i/o; in expanded modes, the pins are us ed for the external buses. in expanded wide m ode, ports a and b are us ed for multiplexed 16-bit data and address buses. pa[7:0] correspond to addr[15:8]/data[15:8]; pb[7:0] corr espond to addr[7:0]/data[7:0]. in expanded narrow mode, ports a and b are used for the16-bit address bus, and an 8-bit data bus is multiplexed with the most significant half of the address bus on port a. in this mode, 16-bit data is handled as two back-to-back bus cycles, one for the high byte fo llowed by one for the low byte. pa[7:0] correspond to a ddr[15:8] and to data[15:8] or data[7:0], depending on the bus cycl e. the state of the address pin should be latched at t he rising edge of e. to al low for maximum address setup time at external devices, a transparent latch should be used.
pinout and signal descriptions signal descriptions mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor pinout and signal descriptions 49 3.5.9 read/write (r/w ) in all modes this pin can be used as general-pur pose i/o and is an input with an active pull-up out of reset. if the read/write function is required it should be enabled by se tting the rdwe bit in the pear register. external writes will not be possibl e until enabled. 3.5.10 low-byt e strobe (lstrb) in all modes this pin can be used as general-pur pose i/o and is an input with an active pull-up out of reset. if the strobe f unction is required, it should be enabled by sett ing the lstre bit in the pear register. this signal is used in write operations and so external low byte writes will not be possible until this function is enabled. this pin is also used as taglo in special expanded modes and is multiplexed with the lstrb function. 3.5.11 instruction queue tracki ng signals (ipi pe1 and ipipe0) these signals are used to track the st ate of the internal instruction execution queue. execution state is ti me-multiplexed on the two signals. refer to development support . 3.5.12 data bus enable (dbe ) the dbe pin (pe7) is an active low signal that will be asserted low during eclk high time. dbe provides separation between output of a multiplexed address and the input of data. when an external address is stretched, dbe is asserted during what woul d be the last quarter cycle of the last eclk cycle of stretch. in expanded modes this pin is used to enable the drive control of external buses during external reads. use of the dbe is controlled by the ndbe bit in the pear register.dbe is enabled out of reset in expanded m odes. this pin has an active pull-up during and after reset in single chip modes.
pinout and signal descriptions technical data mc68hc9 12d60a ? rev. 3.1 50 pinout and signal descriptions freescale semiconductor 3.5.13 inverted eclk (eclk ) the eclk pin (pe7) can be used to latch the address for de- multiplexing. it has the same behavior as the ecl k, except is inverted. in expanded modes this pin is used to enable the drive control of external buses during external re ads. use of the eclk is controlled by the ndbe and dbene bits in th e pear register. 3.5.14 calibrat ion reference (cal) the cal pin (pe7) is the output of the slow mode programmable clock divider, slwclk, and is used as a ca libration referenc e. the slwclk frequency is equal to th e crystal frequency out of reset and always has a 50% duty. if the dbe function is enabled it will override the enabled cal output. the cal pin output is disabled by cl earing cale bit in the pear register. 3.5.15 clock generation module test (cgmtst) the cgmtst pin (pe6) is the output of the clocks tested when cgmte bit is set in pear regi ster. the pipoe bit must be cleared for the clocks to be tested. 3.5.16 test this pin is used for fact ory test purposes. it is recommended that this pin is not connected in the applicatio n, but it may be bonded to 5.5 v max without issue. neve r apply voltage hi gher than 5.5 v to this pin. table 3-2. mc68hc912d60a signal description summary pin name pin number description 80-pin 112-pin extal 35 47 crystal driver and external clock input pins. xtal 36 48 reset 34 46 an active low bidirecti onal control signal, reset acts as an input to initialize the mcu to a known start-up state, and an output when cop or clock monitor causes a reset.
pinout and signal descriptions signal descriptions mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor pinout and signal descriptions 51 addr[7:0] data[7:0] 23?16 31?24 external bus pins share function with general-purpose i/o ports a and b. in single chip modes, the pins can be used for i/o. in expanded modes, the pins are used for the external buses. addr[15:8] data[15:8] 48?41 64?57 dbe 25 36 data bus control and, in expanded mode, enables the drive control of external buses during external reads. eclk 25 36 inverted eclk used to latch the address. cal 25 36 cal is the output of the slow mode programmable clock divider, slwclk, and is used as a calibration reference for functions such as time of day. it is overridden when dbe function is enabled. it always has a 50% duty cycle. cgmtst 26 37 clock generation module test output. modb/ ipipe1, moda/ ipipe0 26, 27 37, 38 state of mode select pins during reset determine the initial operating mode of the mcu. after reset, modb and moda can be configured as instruction queue tracking signals ipipe1 and ipipe0 or as general- purpose i/o pins. eclk 28 39 e clock is the output connection for the external bus clock. eclk is used as a timing reference and for address demultiplexing. lstrb / tag l o 37 53 low byte strobe (0 = low byte valid), in all modes this pin can be used as i/o. the low strobe function is the exclusive-nor of a0 and the internal sz8 signal. (the sz8 internal signal indicates the size 16/8 access.) pin function taglo used in instruction tagging. see development support . r/w 38 54 indicates direction of data on expansion bus. shares function with general- purpose i/o. read/write in expanded modes. irq 39 55 maskable interrupt request input provides a means of applying asynchronous interrupt requests to the mcu. either falling edge- sensitive triggering or level-sensitiv e triggering is program selectable (intcr register). xirq 40 56 provides a means of requesting asynchronous nonmaskable interrupt requests after reset initialization smodn/bk gd/taghi 15 23 single-wire background interface pin is dedicated to the background debug function. during reset, this pin determines special or normal operating mode. pin function taghi used in instruction tagging. see development support . pw[3:0] 80, 1?3 112, 1?3 pulse width modulator channel outputs. ss 70 96 slave select output for spi master mode, input for slave mode or master mode. sck 69 95 serial clock for spi system. table 3-2. mc68hc912d60a signal description summary pin name pin number description 80-pin 112-pin
pinout and signal descriptions technical data mc68hc9 12d60a ? rev. 3.1 52 pinout and signal descriptions freescale semiconductor 3.6 port signals the mc68hc912d60a incorporates ei ght ports which are used to control and access the various de vice subsystems. when not used for these purposes, port pins may be used for general-purpose i/o. in addition to the pins described below, each port consists of a data register sdo/mosi 68 94 master out/slave in pin for serial peripheral interface sdi/miso 67 93 master in/slave out pin for serial peripheral interface txd1 66 92 sci1 transmit pin rxd1 65 91 sci1 receive pin txd0 64 90 sci0 transmit pin rxd0 63 89 sci0 receive pin ioc[7:0] 14?11, 7?4 18?15, 7?4 pins used for input capture and output compare in the timer and pulse accumulator subsystem. an1[7:0] n/a 84/82/80/78/ 76/74/72/70 analog inputs for the analog-to-digital conversion module 1 an0[7:0] 60?53 83/81/79/77/ 75/73/71/69 analog inputs for the analog-to-digital conversion module 0 test 71 97 used for factory test purposes. do not connect in the application; may be bonded to 5.5 v max. txcan 72 104 mscan transmit pin. leave unconnected if mscan is not used. rxcan 73 105 mscan receive pin. pin has internal pull-up; where mscan module is not used, do not tie to vss. kwg[6:0] 8 (kwg4 only) 9?11, 19?22 key wake-up and general purpose i/o; can cause an interrupt when an input transitions from high to low. on 80-pin qfp all 8 i/o should be initialised. pgupd (1) 13 defines if i/o port resistive load is a pull-up or a pull-down, when enabled. kwh[7:0] 24 (kwh4 only) 32?35, 49?52 key wake-up and general purpose i/o; can cause an interrupt when an input transitions from high to low. on 80-pin qfp all 8 i/o should be initialised. phupd (2) 41 defines if i/o port resistive load is a pull-up or a pull-down, when enabled. 1. in the 80-pin version pgupd is connected internally to vdd 2. in the 80-pin version phupd is connected internally to vss table 3-2. mc68hc912d60a signal description summary pin name pin number description 80-pin 112-pin
pinout and signal descriptions port signals mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor pinout and signal descriptions 53 which can be read and writ ten at any time, and, with the exception of port ad0, port ad1 (avail able only in 112tqfp), pe[1:0], rxcan and txcan, a data direction re gister which controls t he direction of each pin. after reset all general purpose i/ o pins are configured as input. 3.6.1 port a port a pins are used for address and data in expanded modes. in single chip modes, the pins can be used as i/ o. the port data register is not in the address map du ring expanded and periphe ral mode operation. when it is in the map, port a can be read or written at anytime. register ddra determines whether each port a pin is an input or output. ddra is not in the ad dress map during exp anded and peripheral mode operation. setting a bi t in ddra makes the co rresponding bit in port a an output; clearing a bit in ddra ma kes the corresponding bit in port a an input. the defaul t reset state of ddra is all zeros. when the pupa bit in the puc r register is set, all port a input pins are pulled-up internally by an active pull-up device. thi s bit has no effect if the port is being used in expanded modes as t he pull-ups are inactive. setting the rdpa bit in r egister rdriv causes al l port a output s to have reduced drive level. rdriv can be wri tten once after rese t. rdriv is not in the address map in pe ripheral mode. refer to bus control and input/output . 3.6.2 port b port b pins are used for address and data in expanded modes. in single chip modes, the pins can be used as i/ o. the port data register is not in the address map du ring expanded and periphe ral mode operation. when it is in the map, port b can be read or written at anytime. register ddrb determines whether each port b pin is an input or output. ddrb is not in the ad dress map during exp anded and peripheral mode operation. setting a bi t in ddrb makes the co rresponding bit in port b an output; clearing a bit in ddrb ma kes the corresponding bit in port b an input. the defaul t reset state of ddrb is all zeros.
pinout and signal descriptions technical data mc68hc9 12d60a ? rev. 3.1 54 pinout and signal descriptions freescale semiconductor when the pupb bit in the puc r register is set, all port b input pins are pulled-up internally by an active pull-up device. thi s bit has no effect if the port is being used in expanded modes as t he pull-ups are inactive. setting the rdpb bit in r egister rdriv causes al l port b output s to have reduced drive level. rdriv can be wri tten once after rese t. rdriv is not in the address map in pe ripheral mode. refer to bus control and input/output . 3.6.3 port e port e pins operate differently from port a and b pins. port e pins are used for bus control signals and inte rrupt service request signals. when a pin is not used for one of these specific functi ons, it can be used as general-purpose i/o. however, two of the pins (pe[1:0]) can only be used for input, and the stat es of these pins can be read in the port data register even when t hey are used for irq and xirq . the pear register determines pin function, and register ddre determines whether each pi n is an input or output when it is used for general-purpose i/o. pear settings override ddre settings. because pe[1:0] are input-only pins , only ddre[7:2] have ef fect. setting a bit in the ddre register ma kes the corresponding bi t in port e an output; clearing a bit in the dd re register makes the co rresponding bit in port e an input. the defaul t reset state of dd re is all zeros. when the pupe bit in the pucr regist er is set, pe7 and pe[3:0] are pulled up by active devices. neither port e nor ddre is in the map in peripheral mode; neither is in the internal map in ex panded modes wi th eme set. setting the rdpe bit in r egister rdriv causes al l port e output s to have reduced drive level. rdriv can be wri tten once after rese t. rdriv is not in the address map in pe ripheral mode. refer to bus control and input/output .
pinout and signal descriptions port signals mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor pinout and signal descriptions 55 3.6.4 port g port g pins are used for key wake-u ps that can be used with the pins configured as inputs or outputs. t he key wake-ups are triggered with a falling edge signal (kwpg). an in terrupt is generated if the corresponding bit is enabled (kwieg). if any of the in terrupts is not enabled, the correspondi ng pin can be used as a general purpose i/o pin. refer to i/o ports with key wake-up . register ddrg determines pin di rection of port g when used for general-purpose i/o. when d drg bits are set, t he corresponding pin is configured for output. on reset th e ddrg bits are cleared and the corresponding pin is configured for input. port pgupd determines what type of resistive load is used for port g input pins when pupg bi t is set in the pucr register. when pgupd pin is low, it loads a pull- down in all port g input pi ns. when pgupd pin is high, it loads a pull-up in all port g input pins. in 80-pin version, the pgupd is connected internally to vdd. the pg4 will have a pull-up. all port g pins should either be defined as outputs or have their pull-ups enabled. setting the rdpg bit in re gister rdriv causes all port g outputs to have reduced drive level. rdriv can be wri tten once after rese t. rdriv is not in the address map in pe ripheral mode. refer to bus control and input/output . 3.6.5 port h port h pins are used for key wake- ups that can be used with the pins configured as inputs or outputs. t he key wake-ups are triggered with a falling edge signal (kwph). an in terrupt is gen erated if the corresponding bit is enabl ed (kwieh). if any of the interrupts is not enabled, the correspondi ng pin can be used as a general purpose i/o pin. refer to i/o ports with key wake-up . register ddrh determines pin dire ction of port h when used for general-purpose i/o. when d drh bits are set, t he corresponding pin is
pinout and signal descriptions technical data mc68hc9 12d60a ? rev. 3.1 56 pinout and signal descriptions freescale semiconductor configured for output. on reset the ddrh bits are cleared and the corresponding pin is configured for input. port phupd determines what type of resistive load is used for port h input pins when puph bit is set in the pucr regi ster. when phupd pin is low, it loads a pull- down in all port h input pins. when phupd pin is high, it loads a pull-up in all port h input pins. in 80-pin version, the phupd is c onnected internally to vss. the ph4 will have a pull-down. all port h pins should either be defined as outputs or have their pull-downs enabled. setting the rdph bit in register rdriv causes all port h outputs to have reduced drive level. rdriv can be wri tten once after rese t. rdriv is not in the address map in pe ripheral mode. refer to bus control and input/output . 3.6.6 port can the mscan12 uses two external pi ns, one input (rxcan) and one output (txcan). the txcan output pi n represents the l ogic level on the can: ?0? is for a dominan t state, and ?1? is for a recessive state. if the mscan is not used, txcan should be left unconnected and, due to an internal pull-up, the rxcan pi n should not be tied to vss. rxcan is on bit 0 of port can, txc an is on bit 1. the remaining six pins of port can, availabl e only in the 112-pin pack age, are controlled by registers in the mscan12 address space. in 80qfp all portcan[2: 7] pins should either be defined as outputs or have their pull-ups enabled. 3.6.7 port ad1 input to the analog-to-digital sub system and general -purpose input. when analog-to-digital functions are not enabled, the port has eight general-purpose input pins, pad1[7:0 ]. the adpu bit in the atd1ctl2 register enables the a/d function.
pinout and signal descriptions port signals mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor pinout and signal descriptions 57 port ad1 pins are inputs; no data direction register is associated with this port. the port has no resistive input loads and no reduced drive controls. refer to analog-to-digital converter . port ad1 is not avail able in the 80-pin package. 3.6.8 port ad0 input to the analog-to-digital sub system and general -purpose input. when analog-to-digital functions are not enabled, the port has eight general-purpose input pins, pad0[7:0 ]. the adpu bit in the atd0ctl2 register enables the a/d function. port ad0 pins are inputs; no data direction register is associated with this port. the port has no resistive input loads and no reduced drive controls. refer to analog-to-digital converter . 3.6.9 port p the four pulse-width modulation c hannel outputs share general-purpose port p pins. the pwm function is enabled with the pwen register. enabling pwm pins takes precedenc e over the general -purpose port. when pulse-width m odulation is not in use, t he port pins may be used for general-purpose i/o. register ddrp determines pin dire ction of port p when used for general-purpose i/o. when d drp bits are set, t he corresponding pin is configured for output. on reset the ddrp bits are cleared and the corresponding pin is configured for input. when the pupp bit in the pwctl register is set, all input pins are pulled up internally by an acti ve pull-up device. pull-u ps are disabled after reset. setting the rdpp bit in the pwctl r egister configures all port p outputs to have reduced drive leve ls. levels are at normal drive capability after reset. the pwctl r egister can be read or wri tten anytime after reset. refer to pulse width modulator .
pinout and signal descriptions technical data mc68hc9 12d60a ? rev. 3.1 58 pinout and signal descriptions freescale semiconductor 3.6.10 port s port s is the 8-bit interf ace to the standard serial interface consisting of the two serial communications interf aces (sci1 and sc i0) and the serial peripheral interface (spi) subsystems. port s pins are available for general-purpose parallel i/o when st andard serial func tions are not enabled. port s pins serve several functi ons depending on the va rious internal control registers. if wo ms bit in the sc0cr1r egister is set, the p- channel drivers of the output buffers are disabled for bits 0 through 1 for the scsi1 (2 thr ough 3 for the sci0). if sw om bit in the sp0cr1 register is set, the p-channel driver s of the output buffers are disabled for bits 4 through 7 (wir e-ored mode). the open dr ain control effects to both the serial and the gen eral-purpose output s. if the rdpsx bits in the purds register are set, the appropriate port s pin drive c apabilities are reduced. if pupsx bits in the purds register are set, the appropriate pull-up device is connected to each port s pin which is programmed as a general-purpose input. if the pin is programmed as a general-purpose output, the pull-up is disconn ected from the pin regar dless of the state of the individual pu psx bits. see multiple serial interface . 3.6.11 port t this port provides eight general-purpose i/o pins when not enabled for input capture and output compare in the timer and pulse accumulator subsystem. the ten bit in the tscr re gister enables the timer function. the pulse accumulator subsystem is enabled with the p aen bit in the pactl register. register ddrt determines pin direct ion of port t when used for general- purpose i/o. when ddrt bits are set, th e corresponding pin is configured for output. on reset the ddrt bits are cleared and the corresponding pin is configured for input. when the pupt bit in the tmsk2 register is set, al l input pins are pulled up internally by an acti ve pull-up device. pull-u ps are disabled after reset.
pinout and signal descriptions port signals mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor pinout and signal descriptions 59 setting the rdpt bit in the tmsk2 r egister configures all port t outputs to have reduced drive leve ls. levels are at normal drive capability after reset. the tmsk2 regist er can be read or written anyt ime after reset refer to enhanced capture timer . table 3-3 . mc68hc912d60a port description summary port name pin numbers data direction register (address) description 80-pin 112-pin port a pa[7:0] 48?41 64?57 in/out ddra ($0002) port a and port b pins are used for address and data in expanded modes. the port data registers are not in the address map during expanded and peripheral mode operation. when in the map, port a and port b can be read or written any time. ddra and ddrb are not in the address map in expanded or peripheral modes. port b pb[7:0] 23?16 31?24 in/out ddrb ($0003) port ad1 pad1[7:0] n/a 84/82/80 /78/76/7 4/72/70 in analog-to-digital converter 1 and general-purpose i/o. port ad0 pad0[7:0] 60?53 83/81/79 /77/75/7 3/71/69 in analog-to-digital converter 0 and general-purpose i/o. port can pcan[7:0] 72, 73 (1) 98?105 in/out general purpose i/o. pcan[1:0] are used with the mscan12 module and cannot be used as i/o. port e pe[7:0] 25?28, 37?40 36?39, 53?56 pe[1:0] in pe[7:2] in/out ddre ($0009) mode selection, bus control signals and interrupt service request signals; or general-purpose i/o. port p pp[7:0] 76?80, 1?3 108?112 , 1?3 in/out ddrp ($0057) general-purpose i/o. pp[3:0] are used with the pulse-width modulator when enabled. port s ps[7:0] 70?63 96?89 in/out ddrs ($00d7) serial communications interfaces 1 and 0 and serial peripheral interface subsystems and general-purpose i/o. port t pt[7:0] 14?11, 7?4 18?15, 7?4 in/out ddrt ($00af) general-purpose i/o when not enabled for input capture and output compare in the timer and pulse accumulator subsystem. 1. in 80-pin qfp package only txcan and rxcan are available. portcan[2:7] pins should ei ther be defined as outputs or have their pull-ups enabled.
pinout and signal descriptions technical data mc68hc9 12d60a ? rev. 3.1 60 pinout and signal descriptions freescale semiconductor 3.6.12 port pull-up pull-down and reduced drive mcu ports can be conf igured for internal pull-up. to reduce power consumption and rfi, the pin outpu t drivers can be configured to operate at a reduced driv e level. reduced drive ca uses a slight increase in transition time depending on loadi ng and should be used only for ports which have a light loading. table 3-4 summarizes the port pull-up/pull- down default status and controls. table 3-4. port pull-up, pu ll-down and reduced drive summary enable bit reduced drive control bit port name resistive input loads register (address) bit name reset state register (address) bit name reset state port a pull-up pucr ($000c) pupa disabled rdriv ($000d) rdpa full drive port b pull-up pucr ($000c) pupb disabled rdriv ($000d) rdpb full drive port e: pe7, pe[3:2] pull-up pucr ($000c) pupe enabled rdriv ($000d) rdpe full drive pe[1:0] pull-up pucr ($000c) pupe enabled ? pe[6:4] none ? rdriv ($000d) rdpe full drive port g pull-up or pull- down (1) pucr ($000c) pupg enabled rdriv ($000d) rdpg full drive port h pull-up or pull- down (2) pucr ($000c) puph enabled rdriv ($000d) rdph full drive port p pull-up pwcont ($0054) pupp disabled pwcont ($0054) rdpp full drive ps[1:0] pull-up purds ($00d9) pups0 disabled purds ($00db) rdps0 full drive ps[3:2] pull-up purds ($00d9) pups1 disabled purds ($00db) rdps1 full drive ps[7:4] pull-up purds ($00d9) pups2 disabled purds ($00db) rdps2 full drive port t pull-up tmsk2 ($008d) pupt disabled tmsk2 ($008d) tdrb full drive portcan[1]: txcan none ? ? portcan[0]: rxcan pull-up always enabled ? port can[7:2] pull-up pctlcan ($013d) pupcan disabled pctlcan ($013d) rdpcan full drive port ad0 none ? ? port ad1 none ? ? 1. pull-up when pgupd input pin is high, pull-down when pgupd input pin is low. in the 80-pin version, pgupd is interna lly tied to vdd, hence pg4 is pulled up. 2. pull-up when phupd input pin is high, pull-down when phupd input pin is low. in the 80-pin version, phupd is internally tied to vss, hence ph4 is pulled down.
mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor registers 61 technical data ? mc68hc912d60a section 4. registers 4.1 contents 4.2 register block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.2 register block the register block can be mapped to any 2k byte boundary within the standard 64k byte address space by manipulating bits reg[15:11] in the initrg register. in itrg establishes the upper five bits of the register block?s 16-bit address. the register blo ck occupies the first 512 bytes of the 2k byte blo ck. default addressing (aft er reset) is indicated in table 4-1 . for additional info rmation refer to operating modes and resource mapping .
registers technical data mc68hc9 12d60a ? rev. 3.1 62 registers freescale semiconductor addressbit 7654321bit 0name $ 0 0 0 0 pa 7 pa 6 pa 5 pa 4 pa 3 pa 2 pa 1 pa 0 porta (1) $0001 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 portb (1) $0002 dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 ddra (1) $0003 ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb (1) $000400000000 reserved (3) $000500000000 reserved (3) $000600000000 reserved (3) $000700000000 reserved (3) $0008 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 porte (2) $0009 dde7 dde6 dde5 dde4 dde3 dde2 0 0 ddre (2) $000a ndbe cgmte pipoe neclk lstre rdwe cale dbene pear (3) $000b smodn modb moda estr ivis ebswai 0 eme mode (3) $000c puph pupg 0 pupe 0 0 pupb pupa pucr (3) $000d 0 rdph rdpg 0 rdpe 0 rdpb rdpa rdriv (3) $000e00000000 reserved (3) $000f00000000 reserved (3) $0010 ram15 ram14 ram13 ram12 ram11 0 0 0 initrm $0011 reg15 reg14 reg13 reg12 reg11 0 0 mmswai initrg $0012 ee15 ee14 ee13 ee12 0 0 0 eeon initee $0013 maprom ndrf rfstr1 rfstr0 exstr1 exstr0 romon28romon32 misc $0014 rtie rswai rsbck reserved rtbyp rtr2 rtr1 rtr0 rtictl $0015rtif0000000rtiflg $0016 cme fcme fcmcop wcop disr cr2 cr1 cr0 copctl $0017bit 7654321bit 0coprst $001800000000reserved $001900000000reserved $001a00000000reserved $001b00000000reserved $001c00000000reserved $001d00000000reserved $001eirqeirqendly00000intcr $001f 1 1 psel5 psel4 psel3 psel2 psel1 0 hprio $0020 bken1 bken0 bkpm 0 bk1ale bk0ale 0 0 brkct0 = reserved or unimplemented bits. table 4-1. mc68hc912d60a regi ster map (sheet 1 of 9)
registers register block mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor registers 63 $0021 0 bkdbe bkmbh bkmbl bk1rwe bk1rw bk0rwe bk0rw brkct1 $0022 bit 15 14 13 12 11 10 9 bit 8 brkah $0023bit 7654321bit 0brkal $0024 bit 15 14 13 12 11 10 9 bit 8 brkdh $0025bit 7654321bit 0brkdl $002600000000reserved $002700000000reserved $0028 pg7 pg6 pg5 pg4 pg3 pg2 pg1 pg0 portg $0029 ph7 ph6 ph5 ph4 ph3 ph2 ph1 ph0 porth $002a ddg7 ddg6 ddg5 ddg4 ddg3 ddg2 ddg1 ddg0 ddrg $002b ddh7 ddh6 ddh5 ddh4 ddh3 ddh2 ddh1 ddh0 ddrh $002c wi2ce kwieg6 kwieg5 kwieg4 kwieg3 kwieg2 kwieg1 kwieg0 kwieg $002d kwieh7 kwieh6 kwieh5 kwieh4 kwieh3 kwieh2 kwieh1 kwieh0 kwieh $002e 0 kwifg6 kwifg5 kwifg4 kwi fg3 kwifg2 kwifg1 kwifg0 kwifg $002f kwifh7 kwifh6 kwifh5 kwifh4 k wifh3 kwifh2 kwifh1 kwifh0 kwifh $0030?$ 0037 unimplemented (4) reserved $0038 0 0 syn5 syn4 syn3 syn2 syn1 syn0 synr $003900000refdv2refdv1refdv0refdv $003a00000000reserved $003blockiflock0000lhiflhomepllflg $003c lockie pllon auto acq 0 pstp lhie nolhm pllcr $003d 0 bcsp bcss 0 0 mcs 0 0 clksel $003e 0 0 sldv5 sldv4 sldv3 sldv2 sldv1 sldv0 slow $003f00000000reserved $0040 con23 con01 pcka2 pcka1 pcka0 pckb2 pckb1 pckb0 pwclk $0041 pclk3 pclk2 pclk1 pclk0 ppol3 ppol2 ppol1 ppol0 pwpol $00420000pwen3pwen2pwen1pwen0pwen $00430bit 654321bit 0pwpres $0044bit 7654321bit 0pwscal0 $0045bit 7654321bit 0pwscnt0 $0046bit 7654321bit 0pwscal1 $0047bit 7654321bit 0pwscnt1 $0048bit 7654321bit 0pwcnt0 $0049bit 7654321bit 0pwcnt1 $004abit 7654321bit 0pwcnt2 addressbit 7654321bit 0name = reserved or unimplemented bits. table 4-1. mc68hc912d60a regi ster map (sheet 2 of 9)
registers technical data mc68hc9 12d60a ? rev. 3.1 64 registers freescale semiconductor $004bbit 7654321bit 0pwcnt3 $004cbit 7654321bit 0pwper0 $004dbit 7654321bit 0pwper1 $004ebit 7654321bit 0pwper2 $004fbit 7654321bit 0pwper3 $0050bit 7654321bit 0pwdty0 $0051bit 7654321bit 0pwdty1 $0052bit 7654321bit 0pwdty2 $0053bit 7654321bit 0pwdty3 $0054 0 0 0 pswai centr rdpp pupp psbck pwctl $0055discrdiscpdiscal00000pwtst $0056 pp7 pp6 pp5 pp4 pp3 pp2 pp1 pp0 portp $0057 ddp7 ddp6 ddp5 ddp4 ddp3 ddp2 ddp1 ddp0 ddrp $005800000000reserved $005900000000reserved $005a00000000reserved $005b00000000reserved $005c00000000reserved $005d00000000reserved $005e00000000reserved $005f00000000reserved $0060 reserved at d 0 c t l 0 $0061 at d 0 c t l 1 $0062 adpu affc aswai djm r r ascie ascif atd0ctl2 $00630000s1cfifofrz1frz0atd0ctl3 $0064 res10 smp1 smp0 prs4 prs3 prs2 prs1 prs0 atd0ctl4 $0065 0 s8c scan mult sc cc cb ca atd0ctl5 $0066scf0000cc2cc1cc0atd0stat0 $0067 ccf7 ccf6 ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 atd0stat1 $0068 sar9 sar8 sar7 sar6 sar5 sar4 sar3 sar2 atd0testh $0069 sar1 sar0 rst tstout tst3 tst2 tst1 tst0 atd0testl $006a?$ 006e 00000000reserved $006f pad07 pad06 pad05 pad04 pad03 pad02 pad01 pad00 portad0 $0070 bit 15 14 13 12 11 10 9 bit 8 adr00h $0071bit 7bit 6000000adr00l addressbit 7654321bit 0name = reserved or unimplemented bits. table 4-1. mc68hc912d60a regi ster map (sheet 3 of 9)
registers register block mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor registers 65 $0072 bit 15 14 13 12 11 10 9 bit 8 adr01h $0073bit 7bit 6000000adr01l $0074 bit 15 14 13 12 11 10 9 bit 8 adr02h $0075bit 7bit 6000000adr02l $0076 bit 15 14 13 12 11 10 9 bit 8 adr03h $0077bit 7bit 6000000adr03l $0078 bit 15 14 13 12 11 10 9 bit 8 adr04h $0079bit 7bit 6000000adr04l $007a bit 15 14 13 12 11 10 9 bit 8 adr05h $007bbit 7bit 6000000adr05l $007c bit 15 14 13 12 11 10 9 bit 8 adr06h $007dbit 7bit 6000000adr06l $007e bit 15 14 13 12 11 10 9 bit 8 adr07h $007fbit 7bit 6000000adr07l $0080 ios7 ios6 ios5 ios4 ios3 ios2 ios1 ios0 tios $0081 foc7 foc6 foc5 foc4 fo c3 foc2 foc1 foc0 cforc $0082 oc7m7 oc7m6 oc7m5 oc7m4 oc7m3 oc7m2 oc7m1 oc7m0 oc7m $0083 oc7d7 oc7d6 oc7d5 oc7d4 oc7d3 oc7d2 oc7d1 oc7d0 oc7d $0084 bit 15 14 13 12 11 10 9 bit 8 tcnt $0085bit 7654321bit 0tcnt $0086 ten tswai tsbck tffca reserved tscr $0087 reserved tqcr $0088 om7 ol7 om6 ol6 om5 ol5 om4 ol4 tctl1 $0089 om3 ol3 om2 ol2 om1 ol1 om0 ol0 tctl2 $008a edg7b edg7a edg6b edg6a edg5b edg5a edg4b edg4a tctl3 $008b edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg0a tctl4 $008c c7i c6i c5i c4i c3i c2i c1i c0i tmsk1 $008d toi 0 pupt rdpt tcre pr2 pr1 pr0 tmsk2 $008e c7f c6f c5f c4f c3f c2f c1f c0f tflg1 $008ftof0000000tflg2 $0090 bit 15 14 13 12 11 10 9 bit 8 tc0 $0091bit 7654321bit 0tc0 $0092 bit 15 14 13 12 11 10 9 bit 8 tc1 $0093bit 7654321bit 0tc1 $0094 bit 15 14 13 12 11 10 9 bit 8 tc2 $0095bit 7654321bit 0tc2 addressbit 7654321bit 0name = reserved or unimplemented bits. table 4-1. mc68hc912d60a regi ster map (sheet 4 of 9)
registers technical data mc68hc9 12d60a ? rev. 3.1 66 registers freescale semiconductor $0096 bit 15 14 13 12 11 10 9 bit 8 tc3 $0097bit 7654321bit 0tc3 $0098 bit 15 14 13 12 11 10 9 bit 8 tc4 $0099bit 7654321bit 0tc4 $009a bit 15 14 13 12 11 10 9 bit 8 tc5 $009bbit 7654321bit 0tc5 $009c bit 15 14 13 12 11 10 9 bit 8 tc6 $009dbit 7654321bit 0tc6 $009e bit 15 14 13 12 11 10 9 bit 8 tc7 $009fbit 7654321bit 0tc7 $00a0 0 paen pamod pedge clk1 clk0 paovi pai pactl $00a1000000paovfpaifpaflg $00a2bit 7654321bit 0pacn3 $00a3bit 7654321bit 0pacn2 $00a4bit 7654321bit 0pacn1 $00a5bit 7654321bit 0pacn0 $00a6 mczi modmc rdmcl iclat flmc mcen mcpr1 mcpr0 mcctl $00a7 mczf 0 0 0 polf3 polf2 polf1 polf0 mcflg $00a80000pa3enpa2enpa1enpa0enicpacr $00a9000000dly1dly0dlyct $00aa novw7 novw6 novw5 novw4 novw3 novw2 novw1 novw0 icovw $00ab sh37 sh26 sh15 sh04 tfmod pacmx bufen latq icsys $00ac00000000reserved $00ad000000tcbyp0timtst $00ae pt7 pt6 pt5 pt4 pt3 pt2 pt1 pt0 portt $00af ddt7 ddt6 ddt5 ddt4 ddt3 ddt2 ddt1 ddt0 ddrt $00b0 0 pben 0000pbovi0pbctl $00b1000000pbovf0pbflg $00b2bit 7654321bit 0pa3h $00b3bit 7654321bit 0pa2h $00b4bit 7654321bit 0pa1h $00b5bit 7654321bit 0pa0h $00b6 bit 15 14 13 12 11 10 9 bit 8 mccnth $00b7bit 7654321bit 0mccntl $00b8 bit 15 14 13 12 11 10 9 bit 8 tc0h $00b9bit 7654321bit 0tc0h addressbit 7654321bit 0name = reserved or unimplemented bits. table 4-1. mc68hc912d60a regi ster map (sheet 5 of 9)
registers register block mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor registers 67 $00ba bit 15 14 13 12 11 10 9 bit 8 tc1h $00bbbit 7654321bit 0tc1h $00bc bit 15 14 13 12 11 10 9 bit 8 tc2h $00bdbit 7654321bit 0tc2h $00be bit 15 14 13 12 11 10 9 bit 8 tc3h $00bfbit 7654321bit 0tc3h $00c0 btst bspl brld sbr12 sbr11 sbr10 sbr9 sbr8 sc0bdh $00c1 sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 sc0bdl $00c2 loops woms rsrc m wake ilt pe pt sc0cr1 $00c3 tie tcie rie ilie te re rwu sbk sc0cr2 $00c4 tdre tc rdrf idle or nf fe pf sc0sr1 $00c5 scswai mie mdl1 mdl0 0 0 0 raf sc0sr2 $00c6r8t8000000sc0drh $00c7 r7/t7 r6/t6 r5/t5 r4/t4 r3/t3 r2/t2 r1/t1 r0/t0 sc0drl $00c8 btst bspl brld sbr12 sbr11 sbr10 sbr9 sbr8 sc1bdh $00c9 sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 sc1bdl $00ca loops woms rsrc m wake ilt pe pt sc1cr1 $00cb tie tcie rie ilie te re rwu sbk sc1cr2 $00cc tdre tc rdrf idle or nf fe pf sc1sr1 $00cdscswai000000rafsc1sr2 $00cer8t8000000sc1drh $00cf r7/t7 r6/t6 r5/t5 r4/t4 r 3/t3 r2/t2 r1/t1 r0/t0 sc1drl $00d0 spie spe swom mstr cpol cpha ssoe lsbf sp0cr1 $00d1000000 spswai spc0 sp0cr2 $00d200000spr2spr1spr0sp0br $00d3spifwcol0modf0000sp0sr $00d4 0 0 0 0 0 0 0 0 reserved $00d5bit 7654321bit 0sp0dr $00d6 ps7 ps6 ps5 ps4 ps3 ps2 ps1 ps0 ports $00d7 dds7 dds6 dds5 dds4 dds3 dds2 dds1 dds0 ddrs $00d8 0 0 0 0 0 0 0 0 reserved $00d9 0 rdps2 rdps1 rdps0 0 pups2 pups1 pups0 purds $00da? $00df 0 0 0 0 0 0 0 0 reserved $00e0? $00ed unimplemented (4) reserved $00ee000000eediv9eediv8eedivh addressbit 7654321bit 0name = reserved or unimplemented bits. table 4-1. mc68hc912d60a regi ster map (sheet 6 of 9)
registers technical data mc68hc9 12d60a ? rev. 3.1 68 registers freescale semiconductor $00ef eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 eedivl $00f0 nobdml noshb reserved fpopen (5) 1 eeswai protlck dmy eemcr $00f1 shprot 1 1 bprot4 bprot3 bprot2 bprot1 bprot0 eeprot $00f200000000reserved $00f3 bulkp 0 auto byte row erase eelat eepgm eeprog $00f40000000lockfee32lck $00f50000000bootpfee32mcr $00f600000000reserved $00f7 0 0 0 feeswai hven 0 eras pgm fee32ctl $00f80000000lockfee28lck $00f90000000bootpfee28mcr $00fa00000000reserved $00fb 0 0 0 feeswai hven 0 eras pgm fee28ctl $00fc? $00ff unimplemented (4) reserved $0100 0 0 cswai synch tlnken slpak slprq sftres cmcr0 $010100000loopbwupmclksrccmcr1 $0102 sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 cbtr0 $0103 samp tseg22 tseg21 tseg20 tseg 13 tseg12 tseg11 tseg10 cbtr1 $0104 wupif rwrnif twrnif rerrif terrif boffif ovrif rxf crflg $0105 wupie rwrnie twrnie rerrie terrie boffie ovrie rxfie crier $0106 0 abtak2 abtak1 abtak0 0 txe2 txe1 txe0 ctflg $0107 0 abtrq2 abtrq1 abtrq0 0 txeie2 txeie1 txeie0 ctcr $0108 0 0 idam1 idam0 0 idhit2 idhit1 idhit0 cidac $0109? $010d unimplemented (4) reserved $010e rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 crxerr $010f txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 ctxerr $0110 ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 cidar0 $0111 ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 cidar1 $0112 ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 cidar2 $0113 ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 cidar3 $0114am7am6am5am4am3am2am1am0cidmr0 $0115am7am6am5am4am3am2am1am0cidmr1 $0116am7am6am5am4am3am2am1am0cidmr2 $0117am7am6am5am4am3am2am1am0cidmr3 $0118 ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 cidar4 addressbit 7654321bit 0name = reserved or unimplemented bits. table 4-1. mc68hc912d60a regi ster map (sheet 7 of 9)
registers register block mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor registers 69 $0119 ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 cidar5 $011a ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 cidar6 $011b ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 cidar7 $011c am7 am6 am5 am4 am3 am2 am1 am0 cidmr4 $011d am7 am6 am5 am4 am3 am2 am1 am0 cidmr5 $011eam7am6am5am4am3am2am1am0cidmr6 $011f am7 am6 am5 am4 am3 am2 am1 am0 cidmr7 $0120? $013c unimplemented (4) reserved $013d000000pupcanrdpcanpctlcan $013e pcan7 pcan6 pcan5 pcan4 pcan3 pcan2 txcan rxcan portcan $013f ddcan7 ddcan6 ddcan5 ddcan4 ddcan3 ddcan2 0 0 ddrcan $0140? $014f receive buffer rxfg $0150? $015f transmit buffer 0 tx0 $0160? $016f transmit buffer 1 tx1 $0170? $017f transmit buffer 2 tx2 $0180? $01df unimplemented (4) reserved $01e0 reserved atd1ctl0 $01e1 reserved atd1ctl1 $01e2 adpu affc aswai djm r r ascie ascif atd1ctl2 $01e30000s1cfifofrz1frz0atd1ctl3 $01e4 res10 smp1 smp0 prs4 prs3 prs2 prs1 prs0 atd1ctl4 $01e5 0 s8c scan mult sc cc cb ca atd1ctl5 $01e6scf0000cc2cc1cc0atd1stat0 $01e7 ccf7 ccf6 ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 atd1stat1 $01e8 sar9 sar8 sar7 sar6 sar5 sar4 sar3 sar2 atd1testh $01e9 sar1 sar0 rst tstout tst3 tst2 tst1 tst0 atd1testl $01ea?$ 01ee 0 0 0 0 0 0 0 0 reserved $01ef pad17 pad16 pad15 pad14 pad13 pad12 pad11 pad10 portad1 addressbit 7654321bit 0name = reserved or unimplemented bits. table 4-1. mc68hc912d60a regi ster map (sheet 8 of 9)
registers technical data mc68hc9 12d60a ? rev. 3.1 70 registers freescale semiconductor $01f0 bit 15 14 13 12 11 10 9 bit 8 adr10h $01f1bit 7bit 6000000adr10l $01f2 bit 15 14 13 12 11 10 9 bit 8 adr11h $01f3bit 7bit 6000000adr11l $01f4 bit 15 14 13 12 11 10 9 bit 8 adr12h $01f5bit 7bit 6000000adr12l $01f6 bit 15 14 13 12 11 10 9 bit 8 adr13h $01f7bit 7bit 6000000adr13l $01f8 bit 15 14 13 12 11 10 9 bit 8 adr14h $01f9bit 7bit 6000000adr14l $01fa bit 15 14 13 12 11 10 9 bit 8 adr15h $01fbbit 7bit 6000000adr15l $01fc bit 15 14 13 12 11 10 9 bit 8 adr16h $01fdbit 7bit 6000000adr16l $01fe bit 15 14 13 12 11 10 9 bit 8 adr17h $01ffbit 7bit 6000000adr17l 1. port a, port b and data direct ion registers ddra, ddrb are not in map in expanded and peripheral modes. 2. port e and ddre not in map in peripheral mode; also not in map in expanded modes with eme set. 3. registers also not in map in peripheral mode. 4. data read at these locations is undefined. 5. the fpopen bit is available only on the 1l02h and late r mask sets. for previous masks, this bit is reserved. addressbit 7654321bit 0name = reserved or unimplemented bits. table 4-1. mc68hc912d60a regi ster map (sheet 9 of 9)
mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor operating modes and resource mapping 71 technical data ? mc68hc912d60a section 5. operating m odes and resource mapping 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.3 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.4 background debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.5 internal resource mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . .77 5.6 memory maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.2 introduction eight possible operatin g modes determine the oper ating configuration of the mc68hc912d60a. each mode has an associated default memory map and external bus configuration. after reset, most system resources can be mapped to other addr esses by writing to the appropriate control registers. 5.3 operating modes the operating mode out of reset is determined by the states of the bkgd, modb, and moda pins during reset. the smodn, modb, and moda bits in the mode register show current operating mode and provide limit ed mode switching during operation.
operating modes and resource mapping technical data mc68hc9 12d60a ? rev. 3.1 72 operating modes and resource mapping freescale semiconductor the states of the bkgd, modb, and moda pins are latched into these bits on the rising edge of the reset signal. there are two basic type s of operating modes: normal modes ? some register s and bits are protected against accidental changes. special modes ? allow greater a ccess to protected control registers and bits for special purposes such as testing and emulation. for operation above 105 c, the mc68hc912d60a (m temperature range product only) is limited to single chip mode s of operation. a system development and debug feature, background debug mode (bdm), is available in all modes. in special si ngle-chip mode, bdm is active immediately after reset. 5.3.1 normal operating modes these modes provide three operati ng configurations. background debugging is available in all three modes , but must first be enabled for some operations by means of a bdm background command, then activated. table 5-1. mode selection bkgd modb moda mode port a port b 1 0 0 normal single chip g.p. i/o g.p. i/o 1 0 1 normal expanded narrow addr/data addr 110 reserved (forced to peripheral) ?? 1 1 1 normal expanded wide addr/data addr/data 0 0 0 special single chip g.p. i/o g.p. i/o 0 0 1 special expanded narrow addr/data addr 0 1 0 special peripheral addr/data addr/data 0 1 1 special expanded wide addr/data addr/data
operating modes and resource mapping operating modes mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor operating modes and resource mapping 73 normal single-chip mode ? there are no ex ternal address and data buses in this mode. the mcu operates as a stand- alone device and all program and data resources are on-chip. external port pins normally a ssociated with address and data buses can be used for general-purpose i/o. normal expanded wide mode ? this is a normal mode of operation in which the expanded bu s is present with a 16-bit data bus. ports a and b are used for the 16-bit multiplexed address/data bus. normal expanded narrow mode ? this is a normal mode of operation in which the expanded bu s is present with an 8-bit data bus. ports a and b are us ed for the16-bit address bus. port a is used as the data bus, multiplexed with addresses. in this mode, 16-bit data is pres ented one byte at a time, the high byte followed by the low by te. the address is automatically incremented on the second cycle. 5.3.2 special operating modes there are three special operating modes that correspond to normal operating modes. these oper ating modes are comm only used in factory testing and system dev elopment. in addition, there is a special peripheral mode, in which an external master, such as an i.c. tester, can control the on-chip peripherals. special single-chip mode ? this mode can be used to force the mcu to active bdm mode to allow system debug through the bkgd pin. there are no external address and data buses in this mode. the mcu operates as a stand-alone device and all program and data space are on-chip. external port pins can be used for general-purpose i/o. special expanded wide mode ? this mode can be used for emulation of norm al expanded wide mode and emulation of normal single-chip mode. ports a and b are used for the 16-bit multiplexed a ddress/data bus.
operating modes and resource mapping technical data mc68hc9 12d60a ? rev. 3.1 74 operating modes and resource mapping freescale semiconductor special expanded narrow mode ? this mode can be used for emulation of normal expand ed narrow mode. ports a and b are used for the16-bi t address bus. port a is used as the data bus, multiplexed with addresses. in this mode, 16-bit data is presented one byte at a time, the high byte followed by the low byte. the address is automatical ly incremented on the second cycle. special peripheral mode ? the cpu is not ac tive in this mode. an external master can control on-chip peripherals for testing purposes. it is not possible to change to or from this mode without goi ng through reset. background debugging should not be used while the m cu is in special peripheral mode as internal bus conflict s between bdm and the external master can cause improper operation of both modes. 5.4 background debug mode background debug m ode (bdm) is an auxiliary operating mode that is used for system development. bdm is implemented in on-chip hardware and provides a full set of debug oper ations. some bdm commands can be executed while the cpu is op erating normal ly. other bdm commands are firmware based, and re quire the bdm firmware to be enabled and active for execution. in special single-chip m ode, bdm is enabl ed and active immediately out of reset. bdm is available in al l other operating modes, but must be enabled before it can be activated. bdm shoul d not be used in special peripheral mode because of potential bus conflicts. once enabled, ba ckground mode can be made active by a serial command sent via the bkgd pin or execution of a cpu12 bgnd instruction. while back ground mode is active, the cpu can interpret special debugging commands, and r ead and write cpu registers, peripheral registers, and locations in memory. while bdm is active, t he cpu executes code loca ted in a sm all on-chip rom mapped to addresses $ff20 to $ff ff, and bdm control registers are accessible at addr esses $ff00 to $ff06. the bdm rom replaces
operating modes and resource mapping background debug mode mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor operating modes and resource mapping 75 the regular system vectors while bdm is active. while bdm is active, the user memory from $ff0 0 to $ffff is not in t he map except through serial bdm commands. mode controls the mc u operating mode and various configuration options. this register is not in the map in peripheral mode smodn, modb, moda ? mode select special, b and a these bits show the current operati ng mode and reflect the status of the bkgd, modb an d moda input pins at the rising e dge of reset. smodn is read anytime . may only be written in special modes (smodn = 0). the firs t write is ignored; modb, moda may be wr itten once in normal modes (smodn = 1). write anytime in special modes (fi rst write is ig nored) ? special peripheral and reserved m odes cannot be selected. bit 7654321bit 0 smodn modb moda estr ivis ebswai 0 eme reset:00011001special single chip reset:00111001special exp nar reset:01011001 peripheral reset:01111001special exp wide reset:10010000normal single chip reset:10110000normal exp nar reset:11110000normal exp wide mode ? mode register $000b
operating modes and resource mapping technical data mc68hc9 12d60a ? rev. 3.1 76 operating modes and resource mapping freescale semiconductor estr ? e clock stretch enable determines if the e clock behaves as a simple free-running clock or as a bus control signal that is active onl y for external bus cycles. estr is always 1 in expanded modes since it is required for address and data bus de-multiplexing and must follow stretched cycles. 0 = e never stretches (always free running). 1 = e stretches high during exte rnal access cycles and low during non-visible internal accesses (ivis=0). normal modes: write onc e; special modes: write anytime. read anytime. ivis ? internal visibility this bit determines whether internal addr, data, r/w and lstrb signals can be s een on the external bus dur ing accesses to internal locations. in special narrow mode if this bit is set and an internal access occurs the data will appear wid e on ports a and b. this serves the same function as the emd bit of the non-multiplexed versions of the hc12 and allows for emulation. vi sibility is not available when the part is operating in a single-chip mode. 0 = no visibility of internal bus operations on external bus. 1 = internal bus oper ations are visible on external bus. normal modes: write onc e; special modes: write anytime except the first time. read anytime. ebswai ? external bus modul e stop in wait control this bit controls access to the external bus in terface when in wait mode. the module will delay before shutting down in wait mode to allow for final bus activity to complete. 0 = external bus and regi sters continue function ing during wait mode. 1 = external bus is sh ut down during wait mode. normal modes: write anytime; special modes: write never. read anytime.
operating modes and resource mapping internal resource mapping mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor operating modes and resource mapping 77 eme ? emulate port e in single-chip mode porte and ddre are always in the map regardless of the st ate of this bit. 0 = porte and ddre are in the memory map. 1 = if in an expanded mode, port e and ddre are removed from the internal memory map. removing the registers from the map allows the user to emulate the function of these registers externally. normal modes: write onc e; special modes: write anytime except the first time. read anytime. 5.5 internal resource mapping the internal register block, ram , and eeprom have default locations within the 64k byte standard addre ss space but may be reassigned to other locations during pr ogram execution by se tting bits in mapping registers initrg, initrm, and init ee. during normal operating modes these registers can be written once. it is advisable to explicitly establish these resource locations during the initialization pha se of program execution, even if default values ar e chosen, in order to protect the registers from inadvertent modification later. writes to the mapping registers go into effect between the cycle that follows the write and t he cycle after that. to assu re that there are no unintended operations, a wr ite to one of these registers should be followed with a nop instruction. if conflicts occur when mapping resource s, the register block will take precedence over the other resour ces; ram or eeprom addresses occupied by the register block will not be avail able for storage. when active, bdm rom takes precedence over other resources, although a conflict between bdm rom and register space is not possible. the following table shows res ource mapping precedence. in expanded modes, all addr ess space not used by in ternal resources is by default external memory. the mc68hc912d60a contains 60k bytes of flash eeprom nonvolatile memory which can be used to store program code or static
operating modes and resource mapping technical data mc68hc9 12d60a ? rev. 3.1 78 operating modes and resource mapping freescale semiconductor data. it is made of the 28k by te fee28 array m apped from $1000 to $7fff at reset and of the 32 k byte fee32 array mapped from $8000 to $ffff at reset. maprom bi t in the misc register allows the swapping of the two flash arrays. 5.5.1 register block mapping after reset the 512 byte register bl ock resides at lo cation $0000 but can be reassigned to any 2k byte boundary within the standard 64k byte address space. mapping of in ternal registers is controlled by five bits in the initrg register. the re gister block occupies t he first 512 bytes of the 2k byte block. reg[15:11] ? internal register map position these bits specify the upper five bits of the 16-bit registers address. normal modes: write once; special modes: write anytime. read anytime. table 5-2. mapping precedence precedence resource 1 bdm rom (if active) 2 register space 3ram 4 eeprom 5 on-chip flash eeprom (mc68hc912d60a) 6 external memory bit 7654321bit 0 reg15 reg14 reg13 reg12 reg11 0 0 mmswai reset: 0 0 0 0 0 0 0 0 initrg ? initialization of internal register position register $0011
operating modes and resource mapping internal resource mapping mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor operating modes and resource mapping 79 mmswai ? memory mapping inte rface stop in wait control this bit controls acce ss to the memory mappi ng interface when in wait mode. normal modes: write any time; special modes: write never. read anytime. 0 = memory mapping inte rface continues to function during wait mode. 1 = memory mapping in terface access is shut down during wait mode. 5.5.2 ram mapping the mc68hc912d60a has 2k byte of fu lly static ram t hat is used for storing instructions, variables, and temporary dat a during program execution. after reset, ram addressi ng begins at loca tion $0000 but can be assigned to any 2k byte boundar y within the stan dard 64k byte address space. mapping of internal ram is controlled by five bits in the initrm register. after reset, the first 512 bytes of ra m have their access inhibited by the presence of the register address space. after initial m cu configuration, it is recommended to map the r egister space at location $0800. ram[15:11] ? internal ram map position these bits specify the upper five bits of the 16 -bit ram address. normal modes: write once; special modes: write anytime. read anytime. bit 7654321bit 0 ram15 ram14 ram13 ram12 ram11 0 0 0 reset:00000000 initrm ? initialization of internal ram position register $0010
operating modes and resource mapping technical data mc68hc9 12d60a ? rev. 3.1 80 operating modes and resource mapping freescale semiconductor 5.5.3 eeprom mapping the mc68hc912d60a has 1k bytes of eeprom which is activated by the eeon bit in the initee register. mapping of internal eeprom is controlled by four bits in the in itee register. after reset eeprom address space begins at location $0c00 but can be mapped to any 4k byte boundary within the st andard 64k byte address space. ee[15:12] ? internal eeprom map position these bits specify the upper four bi ts of the 16-bit eeprom address. normal modes: write once; special modes: write anytime. read anytime. eeon ? internal e eprom on (enabled) this bit is forced to one in single-chip modes. read or write anytime. 0 = removes the eepro m from the map. 1 = places the on-chip eeprom in the memory map at the address selected by ee[15:12]. bit 7654321bit 0 ee15 ee14 ee13 ee12 0 0 0 eeon reset:00000001 initee ? initialization of internal eeprom position register $0012
operating modes and resource mapping internal resource mapping mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor operating modes and resource mapping 81 5.5.4 miscellaneous syst em control register additional mapping and exte rnal resource controls are available. to use external resources the part must be operated in on e of the expanded modes. normal modes: write onc e; special modes: write anytime. read anytime. maprom ? map loc ation of rom this bit is used to swap the locati on of the on-chip flash eeprom. 0 = 28k byte array is mapped from $1000 to $7fff, 32k byte array is mapped from $8000 to $ffff. 1 = 28k byte is mapped from $9000 to $ffff, 32k byte array is mapped from $0000 to $7fff. ndrf ? narrow data bus for register-following map space this bit enables a narrow bus feature for t he 512 byte register- following map. this is useful for accessing 8-bit peripherals and allows 8-bit and 16-bit external memory devic es to be mixed in a system. in expanded narrow (eight bit) modes, single chip modes, and peripheral mode, th is bit has no effect. 0 = makes register-following map s pace act as a full 16 bit data bus. 1 = makes the register -following map space ac t the same as an 8 bit only external data bus (data onl y goes through port a externally). the register-following space is mapped from $0200 to $03ff after reset, which is next to the register map. if the registers are moved this space follows. bit 7654321bit 0 maprom ndrf rfstr1 rfstr0 exstr1 exstr0 romon28 romon32 reset: 0 0 0 0 1 1 0 0 exp modes reset: 0 0 0 0 1 1 1 1 sc modes misc ? miscellaneous mapping control register $0013
operating modes and resource mapping technical data mc68hc9 12d60a ? rev. 3.1 82 operating modes and resource mapping freescale semiconductor rfstr1, rfstr0 ? regi ster following stretch this two bit field determines the amount of clock stretch on accesses to the 512 byte register following m ap. it is valid regardless of the state of the ndrf bit. in single chip and peri pheral modes this bit has no meaning or effect. exstr1, exstr0 ? external access stretch this two bit field determines the amount of clock stretch on accesses to the external address space. in single chip and peripheral modes this bit has no meaning or effect. romon28, romon32 ? enable bits for rom these bits are used to enable t he flash eeprom arrays fee28 and fee32 respectively. 0 = corresponding flash eeprom arra y disabled from the memory map. 1 = corresponding flash eeprom array enabled in the memory map. table 5-3. rfstr stretch bit definition rfstr1 rfstr0 number of e clocks stretched 00 0 01 1 10 2 11 3 table 5-4. exstr stretch bit definition exstr1 exstr0 number of e clocks stretched 00 0 01 1 10 2 11 3
operating modes and resource mapping memory maps mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor operating modes and resource mapping 83 5.6 memory maps the following diagrams illus trate the memory m ap for each mode of operation immediately after reset . figure 5-1 . mc68hc912d60a memory map $01ff registers (mappable to any 2k space) 2k bytes ram (mappable to any 2k space) expanded normal single chip special single chip $0000 $07ff $0000 1k bytes eeprom (mappable to any 4k space) $0fff $0c00 vectors vectors bdm (if active) $ffff $ff00 28k flash eeprom (fee28) $7fff $1000 $ffff $8000 32k flash eeprom (fee32) $e000 ?$ffff protected boot ext $6000 - $7fff protected boot $0000 $0800 $0c00 $1000 $8000 $ff00 $ffff $0200 vectors
operating modes and resource mapping technical data mc68hc9 12d60a ? rev. 3.1 84 operating modes and resource mapping freescale semiconductor
mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor bus control and input/output 85 technical data ? mc68hc912d60a section 6. bus control and input/output 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.3 detecting access type from external signals . . . . . . . . . . . . . 85 6.4 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 6.2 introduction internally the mc68h c912d60a has full 16 -bit data paths, but depending upon the oper ating mode and cont rol registers, the external multiplexed bus may be 8 or 16 bits. there are cases where 8-bit and 16-bit accesses can appear on adj acent cycles using the lstrb signal to indicate 8- or 16-bit data. it is possible to have a mix of 8 and 16 bit peripherals attached to the external multiplexed bus, using the nd rf bit in the misc register while in expanded wide modes. 6.3 detecting access type from external signals the external signals lstrb , r/w , and a0 can be us ed to determine the type of bus access that is taking place. accesse s to the internal ram module are the only type of access that produce lstrb =a0=1, because the internal ram is specif ically designed to allow misaligned 16-bit accesses in a single cycle. in these cases the data for the address
bus control and input/output technical data mc68hc9 12d60a ? rev. 3.1 86 bus control and input/output freescale semiconductor that was accessed is on the low half of the data bus and the data for address + 1 is on the hi gh half of the data bus. 6.4 registers not all registers are vi sible in the mc68hc912d 60a memory map under certain conditions. in special peri pheral mode the fi rst 16 registers associated with bus expansion are removed from t he memory map. in expanded modes, some or all of port a, port b, and port e are used for expansion buses and co ntrol signals. in order to allow emulation of the single-chip functions of these ports, some of these registers must be rebuilt in an external port replacement unit. in any expanded mode, port a, and port b, are used fo r address and data lines so registers for these ports, as well as the data direction r egisters for these ports, are removed from the on-chip me mory map and become external accesses. in any expanded mode, port e pins ma y be needed for bus control (e.g., eclk, r/w ). to regain the singl e-chip functions of port e, the emulate port e (eme) control bit in the mode r egister may be set. in this special case of expanded mode and eme set, porte and ddre registers are removed from the on-chip memory map and become external accesses so port e may be rebuilt externally. figure 6-1. access type vs. bus control pins lstrb a0 r/w type of access 1 0 1 8-bit read of an even address 0 1 1 8-bit read of an odd address 1 0 0 8-bit write of an even address 0 1 0 8-bit write of an odd address 0 0 1 16-bit read of an even address 111 16-bit read of an odd address (low/high data swapped) 0 0 0 16-bit write to an even address 110 16-bit write to an even address (low/high data swapped)
bus control and input/output registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor bus control and input/output 87 bits pa[7:0] are associ ated respectively with addresses addr[15:8], data[15:8] and data[7:0], in narrow mode. when this port is not used for external ad dresses such as in single-ch ip mode, these pins can be used as general-purpose i/o. ddra deter mines the primary direction of each pin. this register is not in the on-chip map in expanded and peripheral modes. read and write anytime. this register deter mines the primary direction for each port a pin when functioning as a general- purpose i/o port. ddra is not in the on-chip map in expanded and peripheral modes. read and write anytime. 0 = associated pin is a high-impedance input 1 = associated pin is an output bit 7654321bit 0 single chip pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 reset: ? ? ? ? ? ? ? ? expanded & periph: addr15/ data15 addr14/ data14 addr13/ data13 addr12/ data12 addr11/ data11 addr10/ data10 addr9/ data9 addr8/ data8 expanded narrow addr15/ data15/ data7 addr14/ data14/ data6 addr13/ data13/ data5 addr12/ data12/ data4 addr11/ data11/ data3 addr10/ data10/ data2 addr9/ data9/ data1 addr8/ data8/ data0 porta ? port a register $0000 bit 7654321bit 0 dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 reset: 00000000 ddra ? port a data direction register $0002
bus control and input/output technical data mc68hc9 12d60a ? rev. 3.1 88 bus control and input/output freescale semiconductor bits pb[7:0] are asso ciated with addresses addr[7:0] and data[7:0] (except in narrow mode) respectively . when this port is not used for external addresses such as in single-chip mode, these pins can be used as general-purpose i/o. ddrb determines the primary direction of each pin. this register is not in the on-chip map in ex panded and peripheral modes. read and write anytime. this register deter mines the primary direction for each port b pin when functioning as a general- purpose i/o port. ddrb is not in the on-chip map in expanded and peripheral modes. read and write anytime. 0 = associated pin is a high-impedance input 1 = associated pin is an output bit 76 5 4 3 2 1bit 0 single chip pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 reset: ? ? ? ? ? ? ? ? expanded & periph: addr7/ data7 addr6/ data6 addr5/ data5 addr4/ data4 addr3/ data3 addr2/ data2 addr1/ data1 addr0/ data0 expanded narrow addr7 addr6 addr5 addr4 addr3 addr2 addr1 addr0 portb ? port b register $0001 bit 7654321bit 0 ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 reset: 00000000 ddrb ? port b data direction register $0003
bus control and input/output registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor bus control and input/output 89 this register is associated with exte rnal bus control si gnals and interrupt inputs, including dat a bus enable (dbe ), mode select (modb/ipipe1, moda/ipipe0), eclk, size (lstrb ), read/write (r/w ), irq , and xirq . when the associated pin is not used for one of these specific functions, the pin can be used as general-purpose i /o. the port e assignment register (pear) selects the function of each pin. ddre determines the primary direction of each port e pi n when configured to be general- purpose i/o. some of these pins have soft ware selectable pull-ups (dbe , lstrb , r/w , irq , and xirq ). a single control bit e nables the pull-ups for all these pins which are configured as inputs. this register is not in the map in peripheral mode or expanded modes when the eme bit is set. read and write anytime. this register deter mines the primary directi on for each port e pin configured as general-purpose i/o. bit 7654321bit 0 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 reset: ? ? ? ? ? ? ? ? alt. pin function dbe or eclk or cal modb or ipipe1 or cgmtst moda or ipipe0 eclk lstrb or bdtagl or taglo r/w irq xirq porte ? port e register $0008 bit 7654321bit 0 dde7 dde6 dde5 dde4 dde3 dde2 0 0 reset:00000000 ddre ? port e data direction register $0009
bus control and input/output technical data mc68hc9 12d60a ? rev. 3.1 90 bus control and input/output freescale semiconductor 0 = associated pin is a high-impedance input 1 = associated pin is an output pe[1:0] are associated with xirq and irq and cannot be c onfigured as outputs. these pins can be read regar dless of whether the alternate interrupt functions are enabled. this register is not in the map in peripheral mode and expanded modes while the eme cont rol bit is set. read and write anytime. the pear register is used to choos e between the general-purpose i/o functions and the alter nate bus control functions of port e. when an alternate control function is select ed, the associated ddre bits are overridden. the reset condition of th is register depends on the mode of operation because bus-control signals are needed im mediately after reset in some modes. in normal single-chip mode, no exte rnal bus contro l signals are needed so all of port e is conf igured for general-purpose i/o. bit 7654321bit 0 ndbe cgmte pipoe neclk lstre rdwe cale dbene reset: 00000000 normal expanded reset: 00101100 special expanded reset: 11010000peripheral reset: 10010000 normal single chip reset: 00101100 special single chip pear ? port e assignment register $000a
bus control and input/output registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor bus control and input/output 91 in normal expanded modes, the reset vector is located in external memory. the dbe and eclk are required for de-multiplexing address and data, but lstrb and r/w are only needed by the system when there are external wr itable resources. theref ore in normal expanded modes, only the dbe and eclk are c onfigured for thei r alternate bus control functions and the ot her bits of port e ar e configured for general- purpose i/o. if the nor mal expanded system needs any other bus-control signals, pear would need to be written before any access that needed the additional signals. in special expanded modes, dbe , ipipe1, ipipe0, e, lstrb , and r/w are configured as bus-control signals. in peripheral mode, the pear register is not a ccessible for reads or writes. however, the cgmte control bi t is reset to one to configure pe6 as a test output fr om the pll module. ndbe ? no data bus enable normal: write once; special: writ e anytime except the first. read anytime. 0 = pe7 is us ed for dbe , external control of data enable on memories, or inverted eclk. 1 = pe7 is the cal func tion if cale bit is se t in pear register or general-purpose i/o. ndbe controls the use of the dbe pin of port e. the ndbe bit has no effect in single chip or peripheral modes. the associated pin will default to the cal function if the cale bit is se t in pear register or otherwise to an i/o. cgmte ? clock generator module testing enable normal: write never; special: writ e anytime except the first. read anytime. 0 = pe6 is gener al-purpose i/o or pipe output. 1 = pe6 is a test signal output fr om the cgm module (no effect in single chip or normal expanded modes). pipoe = 1 overrides this function and fo rces pe6 to be a pipe status output signal.
bus control and input/output technical data mc68hc9 12d60a ? rev. 3.1 92 bus control and input/output freescale semiconductor pipoe ? pipe status signal output enable normal: write once; special: writ e anytime except the first time. read anytime. 0 = pe[6:5] are general- purpose i/o (if cgmte = 1, pe6 is a test output signal from the cgm module). 1 = pe[6:5] are outputs and indicate the state of the instruction queue (only effective in expanded modes). neclk ? no external e clock normal single chip: write once; spec ial single chip: write anytime; all other modes: write never. read anyti me. in peripheral mode, e is an input and in all other m odes, e is an output. 0 = pe4 is the exte rnal eclk pin subject to the following limitation: in single-chip modes, to get an eclk output signal, it is necessary to have estr = 0 in addition to neclk = 0. 1 = pe4 is a general -purpose i/o pin. lstre ? low strobe (lstrb ) enable normal: write once; special: writ e anytime except the first time. read anytime. this bit has no effect in single-chip modes or normal expanded narrow mode. 0 = pe3 is a general -purpose i/o pin. 1 = pe3 is configur ed as the lstrb bus-control output, provided the mcu is not in single ch ip or normal expanded narrow modes. lstrb is used during external writes. after reset in normal expanded mode, lstrb is disabled. if needed, it should be enabled before external writes. external r eads do not normally need lstrb because all 16 data bits can be driven even if the mcu only needs 8 bits of data. in normal expanded narrow mode this pin is reset to an output driving high allowing the pin to be an outpu t while in and immediately after reset. taglo is a shared functi on of the pe3/lstrb pin. in special expanded modes with lstre set and the bdm tagging on, a zero at the falling edge of e tags the instruction wo rd low byte bei ng read into the instruction queue.
bus control and input/output registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor bus control and input/output 93 rdwe ? read/write enable normal: write once; special: writ e anytime except the first time. read anytime. this bit has no ef fect in single-chip modes. 0 = pe2 is a general -purpose i/o pin. 1 = pe2 is configured as the r/w pin. in single chip modes, rdwe has no effect and pe2 is a general-purpose i/o pin. r/w is used for external writes. af ter reset in normal expanded mode, it is disabled. if needed it sh ould be enabled before any external writes. cale ? calibration reference enable read and write anytime. 0 = calibration reference is disabled and pe7 is general-purpose i/o in single chip or peripheral modes or if the ndbe bit is set. 1 = calibration reference is enabled on pe7 in single chip and peripheral modes or if the ndbe bit is set. dbene ? dbe or inverted e clock on port e[7] normal modes: write onc e. special modes: write anytime except the first; read anytime. dbene controls which signal is output on pe7 when ndbe control bit is cleared. the inverted eclk out put can be used to latch the address for demultiplexing. it has the same behaviour as the eclk, except it is inverted. please note t hat in the case of idle expansion bus, the ?not eclk? signal could stay high for many cycles. the dbne bit has no effe ct in single chip or peripheral modes and pe7 is defaulted to the cal function if the cale bit is set in the pear register or to an i/o otherwise. 0 = pe7 pin used for dbe external control of data enable on memories in expanded m odes when ndbe = 0 1 = pe7 pin used for inverted eclk output in expanded modes when ndbe = 0
bus control and input/output technical data mc68hc9 12d60a ? rev. 3.1 94 bus control and input/output freescale semiconductor these bits select pull-up resistors for any pin in the corresponding port that is currently configur ed as an input. this register is not in the map in peripheral mode. read and write anytime. puph ? pull-up or pull -down port h enable 0 = port h pull-ups are disabled. 1 = enable pull-up/down devices for all port h input pins. pupg ? pull-up or pu ll-down port g enable 0 = port g pull-ups are disabled. 1 = enable pull-up/down devices for all port g input pins. pupe ? pull-up port e enable 0 = port e pull-ups on pe7 and pe[3:0] are disabled. 1 = enable pull-up devices for po rt e input pins pe7 and pe[3:0]. pupb ? pull-up port b enable 0 = port b pull-ups are disabled. 1 = enable pull-up devices for all port b input pins. this bit has no effect if port b is being used as part of the address/data bus (the pull-ups are inactive). pupa ? pull-up port a enable 0 = port a pull-ups are disabled. 1 = enable pull-up devices for all port a input pins. this bit has no effect if port a is being used as part of the address/data bus (the pull-ups are inactive). bit 7654321bit 0 puph pupg 0 pupe 0 0 pupb pupa reset: 1 1 0 1 0 0 0 0 pucr ? pull-up control register $000c
bus control and input/output registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor bus control and input/output 95 these bits select reduced drive for the associat ed port pins. this gives reduced power consumpti on and reduced rf i with a slight increase in transition time (depending on loading). the reduced driv e function is independent of which f unction is being used on a particular port. this register is not in t he map in peripheral mode. normal: write once; spec ial: write anyti me except the first time. read anytime. rdph ? reduced drive of port h 0 = all port h output pi ns have full drive enabled. 1 = all port h output pins have reduced drive capability. rdpg ? reduced dr ive of port g 0 = all port g output pins have full drive enabled. 1 = all port g output pins have reduced drive capability. rdpe ? reduced drive of port e 0 = all port e output pi ns have full drive enabled. 1 = all port e output pins have reduced drive capability. rdpb ? reduced drive of port b 0 = all port b output pi ns have full drive enabled. 1 = all port b output pins have reduced drive capability. rdpa ? reduced drive of port a 0 = all port a output pi ns have full drive enabled. 1 = all port a output pins have reduced drive capability. bit 7654321bit 0 0 rdph rdpg 0 rdpe 0 rdpb rdpa reset: 0 0 000000 rdriv ? reduced drive of i/o lines $000d
bus control and input/output technical data mc68hc9 12d60a ? rev. 3.1 96 bus control and input/output freescale semiconductor
mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor flash memory 97 technical data ? mc68hc912d60a section 7. flash memory 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.3 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 7.4 flash eeprom control bl ock . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.5 flash eeprom arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.6 flash eeprom registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.7 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.8 programming the flash eep rom . . . . . . . . . . . . . . . . . . . . . 101 7.9 erasing the flash eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.10 stop or wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.11 flash protection bit fpop en . . . . . . . . . . . . . . . . . . . . . . . . . 104 7.2 introduction the two flash eeprom modules (3 2-kbyte and 28-kbyte) for the mc68hc912d60a serve as electrical ly erasable and programmable, non-volatile rom emulation memory . the modules can be used for program code that must either exec ute at high spee d or is frequently executed, such as operating system kernels and standard subroutines, or they can be used for static data which is read frequently. the flash eeprom is ideal for pr ogram storage for singl e-chip applications allowing for field reprogramming.
flash memory technical data mc68hc9 12d60a ? rev. 3.1 98 flash memory freescale semiconductor 7.3 overview the flash eeprom array is arranged in a 16-bit configuration and may be read as either bytes, aligned words or misali gned words. access time is one bus cycle for byte and ali gned word access and two bus cycles for misaligned word operations. the flash eeprom module s upports bulk erase only. each flash eeprom m odule has hardware inte rlocks which protect stored data from accide ntal corruption. an erase- and program- protected 8-kbyte block for boot routines is loca ted at $6000?$7fff or $e000?$ffff depending up on the mapped location of the flash eeprom arrays. on 1l02h and later ma sk sets, an optional pr otection scheme is supported to protect the entire two flash eeprom modules (32-kbyte and 28-kbyte) against accident program or erase. this is achieved using the protection bit fpop en in eeprom eemcr (see 7.11 flash protection bit fpopen ). 7.4 flash eeprom control block a 4-byte register block for each module controls the flash eeprom operation. configuration info rmation is specified and programmed independently from the contents of the fl ash eeprom array. after reset, the control register bl ock for the 32k flash eeprom array (fee32) is located from addre sses $00f4 to $00f7 and for the 28k flash eeprom array (fee2 8) from $00f8 to $00fb. 7.5 flash eeprom arrays after reset, the 32k flash eeprom ar ray is located from addresses $8000 to $ffff and the 28k flash eeprom arra y is from $1000 to $7fff. in expanded modes, the flash eeprom arrays ar e turned off. the flash eeprom can be m apped to an alternat e address range. see operating modes and resource mapping .
flash memory flash eeprom registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor flash memory 99 7.6 flash eeprom registers in normal modes the lock bit c an only be written once after reset. lock ? lock register bit 0 = enable write to feemcr register 1 = disable write to feemcr register this register controls the operation of the flash eeprom array. bootp cannot be changed when the lock control bit in the feelck register is set or if hven or pgm or eras in the feec tl register is set . bootp ? boot protect the boot blocks are locat ed at $6000?$7fff and $e000?$ffff for each flash eeprom module. 0 = enable erase and program of 8k byte boot block 1 = disable erase and program of 8k byte boot block this register c ontrols the programming and erasure of the flash eeprom. fee32lck/fee28lck ? flash eeprom lock control register $00f4/$00f8 bit 7 6 5 4 3 2 1 bit 0 0 0 0 0 0 0 0 lock reset: 0 0 0 0 0 0 0 0 fee32mcr/fee28mcr ? flash eeprom module configuration register $00f5/$00f9 bit 7 6 5 4 3 2 1 bit 0 0 0 0 0 0 0 0 bootp reset: 0 0 0 0 0 0 0 1 fee32ctl/fee28ctl ? flash eeprom control register $00f7/$00fb bit 7 6 5 4 3 2 1 bit 0 0 0 0 feeswai hven 0 eras pgm reset: 0 0 0 0 0 0 0 0
flash memory technical data mc68hc9 12d60a ? rev. 3.1 100 flash memory freescale semiconductor feeswai ? flash eeprom stop in wait control 0 = do not halt flash eeprom clock when the part is in wait mode. 0 = halt flash eeprom clock wh en the part is in wait mode. hven ? high-voltage enable this bit enables the charge pump to supply high voltages for program and erase operations in the array. hven can only be set if either pgm or eras are set and the proper sequence for program or erase is followed. 0 = disables high voltage to array and charge pump off 1 = enables high voltage to array and charge pump on eras ? erase control this bit configures the memory for eras e operation. eras is interlocked with the pgm bit such t hat both bits ca nnot be equal to 1 or set to1 at the same time. 0 = erase operation is not selected. 1 = erase operation selected. pgm ? program control this bit configures t he memory for program operation. pgm is interlocked with the eras bit such t hat both bits cannot be equal to 1 or set to1 at the same time. 0 = program operation is not selected. 1 = program operation selected. 7.7 operation the flash eeprom can c ontain program and data. on reset, it can operate as a bootstrap memory to provide the cpu with internal initialization information during the reset sequence. 7.7.1 bootstrap oper ation single-chip mode after reset, the cpu controlling th e system will begin booting up by fetching the first program address fr om address $fffe.
flash memory programming the flash eeprom mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor flash memory 101 7.7.2 normal operation the flash eeprom allo ws a byte or aligned word read in o ne bus cycle. a misaligned word read requires an additional bus cycle. the flash eeprom array responds to read operations only. write operations are ignored. 7.7.3 program/erase operation an unprogrammed flash ee prom bit has a logic state of one. a bit must be programmed to change its state from one to zero. erasing a bit returns it to a logic one. the flash eeprom has a minimum program/erase life of 100 cycles. programming or erasing the flash eeprom is accomplished by a series of cont rol register writes. the flash eeprom must be complete ly erased prior to programming final data values. programming and erasing of flash lo cations cannot be performed by code being executed from the flas h memory. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. do not exceed t fpgm maximum (40 s). 7.8 programming the flash eeprom programming the flash ee prom is done on a row basis. a row consists of 32 consecutive words (64 bytes) with rows starting from addresses $xx00, $xx40, $xx80 and $xxc0. when writing a row care should be taken not to writ e data to addresse s outside of the ro w. programming is restricted to aligned word i.e. data writes to select rows/blocks for programming/erase should be to even adresses and writes to any row for programming should be to aligned words.
flash memory technical data mc68hc9 12d60a ? rev. 3.1 102 flash memory freescale semiconductor use this step-by-step procedure to program a row of flash memory. 1. set the pgm bit. this configur es the memory for program operation and enables the latchi ng of address and data for programming. 2. write to any aligned word fl ash address within the row address range desired (with any data) to select the row. 3. wait for a time, t nvs (min. 10 s). 4. set the hven bit. 5. wait for a time, t pgs (min. 5 s). 6. write one data word (two bytes) to the next alig ned word flash address to be programmed. if boot p is asserted, an attempt to program an address in the boot block will be ignored. 7. wait for a time, t fpgm (min. 30 s ? max. 40 s). 8. repeat steps 6 and 7 until all the words within the row are programmed. 9. clear the pgm bit. 10. wait for a time, t nvh (min. 5 s). 11. clear the hven bit. 12. after time, t rcv (min 1 s), the memory can be accessed in read mode again. this program sequence is repeated th roughout the memory until all data is programmed. for minimum ov erall programming time and least program disturb effect, the sequence should be part of an intelligent operation which it erates per row.
flash memory technical data mc68hc9 12d60a ? rev. 3.1 103 flash memory freescale semiconductor 7.9 erasing the flash eeprom the following sequence demonstrat es the recommended procedure for erasing any of the flash eeprom array. 1. set the eras bit. 2. write to any valid a ligned word address in the flash array. the data written and the address writt en are not importa nt. the boot block will be erased only if the control bit bootp is negated. 3. wait for a time, t nvs (min. 10 s). 4. set the hven bit. 5. wait for a time, t eras (8ms). 6. clear the eras bit. 7. wait for a time, t nvhl (min. 100 s). 8. clear the hven bit. 9. after time, t rcv (min 1 s), the memory can be accessed in read mode again. 7.10 stop or wait mode when stop or wait comm ands are executed, t he mcu puts the flash eeprom in stop or wait mode. in these modes the fl ash module will cease erasure or progr amming immediately. caution: it is advised not to enter stop or wait modes when program or erase operation of the flash array is in progress.
flash memory technical data mc68hc9 12d60a ? rev. 3.1 104 flash memory freescale semiconductor 7.11 flash protection bit fpopen the fpopen bit is loca ted in eemcr ? eeprom module configuration register, bit 4. fpopen ? opens the flash ar ray for program or erase 0 = the whole flash array (32-kb yte and 28-kbyte) is protected. 1 = the whole flash ar ray (32-kbyte and 28-kb yte) is enabled for program or erase fpopen can be read at anytime. fpopen can be written only to ?0? for protection but not to ?1? for un- protect in normal mode. fpopen can be written ?0? and ?1? in special mode only. fpopen is loaded at reset fr om eeprom shadow word bit 4. when fpopen is cleared to ?0 ?, the flash array cannot be reprogrammed in normal modes. caution: programming the nvm fpopen bit in the shadow word ($_fc0, bit 4) means that the fpopen bit in t he eemcr register will always be ?0? in normal modes. the flash array c an no longer be modified in normal modes.
mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor eeprom memory 105 technical data ? mc68hc912d60a section 8. eeprom memory 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.3 eeprom selective write more zeros . . . . . . . . . . . . . . . . . . 106 8.4 eeprom programmer? s model . . . . . . . . . . . . . . . . . . . . . . .107 8.5 eeprom control registers . . . . . . . . . . . . . . . . . . . . . . . . . . 108 8.6 program/erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.7 shadow word mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.8 programming eedivh and eedivl registers. . . . . . . . . . . . 116 8.2 introduction the mc68hc912d60a eeprom nonvolatil e memory is arranged in a 16-bit configuration. the eeprom array may be re ad as either bytes, aligned words or misaligned words. access times are one bus cycle for byte and aligned word access and two bus cycles fo r misaligned word operations. programming is by byte or aligned word. attempts to program or erase misaligned words will fail. only the lower byte will be latched and programmed or erased. programming and erasing of th e user eeprom can be done in normal modes. each eeprom byte or aligned word must be erased before programming. the eeprom module supports by te, aligned word, row (32 bytes) or bulk erase, all usi ng the internal charge pump. the erased state is $ff. the e eprom module ha s hardware interlocks which protect stored data from corrupti on by accidentally enabling the
eeprom memory technical data mc68hc9 12d60a ? rev. 3.1 106 eeprom memory free scale semiconductor program/erase voltag e. programming voltage is derived from the internal v dd supply with an in ternal charge pump. 8.3 eeprom selective write more zeros the eeprom can be programmed such th at one or multiple bits are programmed (written to a lo gic ?0?) at a time. ho wever, the user should never program any bit more than once before erasing the entire byte. in other words, the user is not allowed to over write a l ogic ?0? with another ?0?. for some applications it may be adv antageous to track more than 10k events with a single byte of eeprom by programmi ng one bit at a time. for that purpose, a special sele ctive bit programmi ng technique is available. an example is shown here. original state of byte = binary 1111:1111 (erased) first event is recorded by programming bit position 0 program write = binary 1111:1110; re sult = binary 1111:1110 second event is recorded by programming bit position 1 program write = binary 1111:1101; re sult = binary 1111:1100 third event is recorded by programming bit position 2 program write = binary 1111:1011; re sult = binary 1111:1000 fourth event is recorded by programming bi t position 3 program write = binary 1111:0111; re sult = binary 1111:0000 events five through eight are re corded in a similar fashion. note that none of the bit locations are actually programmed more than once although the byte wa s programmed eight times. when this technique is ut ilized, a program / er ase cycle is defined as multiple writes (up to eight) to a unique locati on followed by a single erase sequence.
eeprom memory eeprom programmer?s model mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor eeprom memory 107 8.4 eeprom programmer?s model the eeprom module consists of two separately addressable sections. the first is an eight-byte memory m apped control register block used for control, testing and configuration of the eeprom array. the second section is the eeprom array itself. at reset, the eight-byte register se ction starts at address $00ec and the eeprom array is located from addr esses $0c00 to $0fff. registers $00ec-$00ed are reserved. read/write access to the memory array section can be enabled or disabled by the eeon control bit in the initee register ($0012). this feature allows the access of memo ry mapped resources that have lower priority than the eeprom memory ar ray. eeprom control registers can be accessed regardless of the state of eeon. for in formation on re- mapping the register block and eep rom address space, refer to operating modes and resource mapping . caution: it is strongly recomm ended to discontinue program /erase operations during wait (when eeswai=1) or stop modes since all program/erase activiti es will be terminated abruptly and considered unsuccessful. for lowest power consumption during wait mode, it is advised to turn off eepgm. the eeprom module contains an ex tra word called shadow word which is loaded at reset into t he eemcr, eedivh and eedivl registers. to program the shadow word, when in special modes (smodn=0), the noshw bit in eemc r register must be cleared. normal programming routines are used to program the shadow word which becomes accessible at address $0fc0-$0fc1 when noshw is cleared. at the next reset the sh adow word data is loaded into the eemcr, eedivh and eedivl regist ers. the shadow word can be protected from being prog rammed or erased by setting the shprot bit of eeprot register.
eeprom memory technical data mc68hc9 12d60a ? rev. 3.1 108 eeprom memory free scale semiconductor a steady internal self-t ime clock is required to provide accurate counts to meet eeprom pr ogram/erase requirements. this clock is generated via a programmable 10-bit prescaler register. automatic program/erase termination is also provided. in ordinary situations, with crystal operating pr operly, the stead y internal self-time clock is derived from th e input clock sour ce (extali). the divider value is as in eedivh:eedivl. in limp -home mode, where the oscillator clock has malfunctioned or is unavailable, the se lf-time clock is derived from the p ll at a nominal f vcomin using a prede fined divider value of $0023. program/erase oper ation is not gua ranteed in limp- home mode. caution: it is strongly recommended that program/erase oper ation is terminated in the event of loss of cr ystal, either by the applic ation software (clearing eepgm & eelat bits) when enteri ng limp home mode or by enabling the clock monitor to generate a clock monitor reset. th is will prevent unnecessary stress on the emulated e eprom during osci llator failure. 8.5 eeprom control registers eedivh ? eeprom modulus divider $00ee bit 7654321bit 0 000000eediv9eediv8 reset: 000000? (1) ? (1) 1. loaded from shadow word. eedivl ? eeprom modulus divider $00ef bit 7654321bit 0 eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 reset: ? (1) ? (1) ? (1) ? (1) ? (1) ? (1) ? (1) ? (1) 1. loaded from shadow word.
eeprom memory eeprom control registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor eeprom memory 109 eediv[9:0] ? prescaler divider loaded from shadow word at reset. read anytime. write once in norma l modes (smodn =1 ) if eelat = 0 and anytime in special mode s (smodn =0) if eelat = 0. the prescaler divider is required to produce a self-tim e clock with a fixed frequency around 28.6 khz for the range of oscillator frequencies. the divider is set so that the oscillato r frequency can be divided by a divide factor that can produce a 35 s +/- 2 s pulse. caution: an incorrect or uninitial ized value on eedi v can result in overstress of eeprom array during program/erase operation. it is also strongly recommend not to program eeprom with osci llator frequencies less than 250 khz. the eediv value is determined by the following formula: note: int[a] denotes the round down integer value of a. program/erase cycles will not be activat ed when eediv = 0. eediv int extali (hz) x 35 6 ? 10 0.5 + [] = table 8-1. eediv selection osc freq. osc period divide factor eediv 16 mhz 62.5ns 560 $0230 8 mhz 125ns 280 $0118 4 mhz 250ns 140 $008c 2 mhz 500ns 70 $0046 1 mhz 1 s 35 $0023 500 khz 2 s 18 $0012 250 khz 4 s 9 $0009
eeprom memory technical data mc68hc9 12d60a ? rev. 3.1 110 eeprom memory free scale semiconductor bits[7:4] are loaded at reset from the eepro m shadow word. note: bit 5 is reserved for test purposes . this location in shadow word should not be programmed otherwise some lo cations of regular eeprom array will not be visible. nobdml ? background debug mode lockout disable 0 = the bdm lockout is enabled. 1 = the bdm lockout is disabled. loaded from shadow word at reset. read anytime. write anytime in special modes (smodn=0). noshw ? shadow word disable 0 = the shadow word is enabled and accessible at address $0fc0-$0fc1. 1 = regular eeprom arra y at address $0fc0-$0fc1. loaded from shadow word at reset. read anytime. write anytime in special modes (smodn=0). when noshw is cleared, the r egular eeprom ar ray bytes at address $0fc0 and $0fc1 are not visible. the shadow word is accessed instead for both read and program/erase operations. bits[7:4] from the high byte of the shadow word , $0fc0, are loaded to eemcr[7:4]. bits[1:0] from the high byte of th e shadow word, $0fc0,are loaded to eedivh[1:0]. bits[7:0] from the low byte of the shadow word, $0fc1,are loaded to ee divl[7:0]. bulk program/erase only applies if shadow word is enabled. note: bit 6 from high byte of shadow word should not be cleared (set to '0') in order to have the full eeprom array visible. if bit 6 from the high byte of the shadow word is cleared then the foll owing thirty bytes $0fc2?$0fff have no meaning and are reserved by freescale. eemcr ? eeprom module configuration $00f0 bit 7654321bit 0 nobdml noshw reserved (1) fpopen (2) 1 eeswai protlck dmy reset: ? (3) ???1100 1. bit 5 has a test function and should not be programmed. 2. the fpopen bit is available only on the 1l02h and later mask sets. for previous masks, this bit is reserved. 3. loaded from shadow word.
eeprom memory eeprom control registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor eeprom memory 111 fpopen ? opens the flash bl ock for program or erase 0 = the whole flash array (32-kb yte and 28-kbyte) is protected. 1 = the whole flash array (32-kb yte and 28-kbyte) is enable for program or erase. loaded from shadow word at rese t. read anytime. write anytime in special modes (smodn=0). writ e once ?0? is allowed in normal mode. eeswai ? eeprom stops in wait mode 0 = the module is not affe cted during wait mode 1 = the module ceases to be clocked during wait mode read and write anytime. note: the eeswai bit should be cleared if the wait mode vectors are mapped in the e eprom array. protlck ? block protect write lock 0 = block protect bits and bulk er ase protection bit can be written 1 = block protect bits are locked read anytime. write once in no rmal modes (smodn = 1), set and clear any time in spec ial modes (smodn = 0). dmy? dummy bit read and write anytime.
eeprom memory technical data mc68hc9 12d60a ? rev. 3.1 112 eeprom memory free scale semiconductor prevents accidental writ es to eeprom. read anytime. write anytime if eepgm = 0 and protlck = 0. shprot ? shadow word protection 0 = the shadow word can be programmed and erased. 1 = the shadow word is protec ted from being programmed and erased. bprot[4:0] ? eeprom block protection 0 = associated eepr om block can be pr ogrammed and erased. 1 = associated eepr om block is protected from being programmed and erased. eeprot ? eeprom block protect $00f1 bit 7654321bit 0 shprot 1 1 bprot4 bprot3 bprot2 bprot1 bprot0 reset: 11111111 table 8-2. 1k byte e eprom block protection bit name block protected block size bprot4 $0c00 to $0dff 512 bytes bprot3 $0e00 to $0eff 256 bytes bprot2 $0f00 to $0f7f 128 bytes bprot1 $0f80 to $0fbf 64 bytes bprot0 $0fc0 to $0fff 64 bytes
eeprom memory eeprom control registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor eeprom memory 113 . bulkp ? bulk erase protection 0 = eeprom can be bulk erased. 1 = eeprom is protected from being bulk or row erased. read anytime. write anytime if eepgm = 0 and protlck = 0. auto ? automatic shutdown of program/era se operation. eepgm is cleared automatically af ter the program/erase cycles are finished when auto is set. 0 = automatic clear of eepgm is disabled. 1 = automatic clear of eepgm is enabled. read anytime. write any time if eepgm = 0. byte ? byte and aligned word erase 0 = bulk or row erase is enabled. 1 = one byte or one al igned word erase only. read anytime. write any time if eepgm = 0. row ? row or bulk er ase (when byte = 0) 0 = erase entire eeprom array. 1 = erase only one 32-byte row. read anytime. write any time if eepgm = 0. byte and row have no ef fect when erase = 0 if byte = 1 only the lo cation specified by the address written to the programming latches will be erased . the operation will be a byte or an aligned word erase depending on the size of written data. eeprog ? eeprom control $00f3 bit 7654321bit 0 bulkp 0 auto byte row erase eelat eepgm reset: 10000000 table 8-3. erase selection byte row block size 0 0 bulk erase entire eeprom array 0 1 row erase 32 bytes 1 0 byte or aligned word erase 1 1 byte or aligned word erase
eeprom memory technical data mc68hc9 12d60a ? rev. 3.1 114 eeprom memory free scale semiconductor erase ? erase control 0 = eeprom configurat ion for programming. 1 = eeprom configur ation for erasure. read anytime. write any time if eepgm = 0. configures the eeprom fo r erasure or programming. unless bulkp is set, erasure is by byte, aligned word, row or bulk. eelat ? eeprom latch control 0 = eeprom set up for normal reads. 1 = eeprom address and data bus latches set up for programming or erasing. read anytime. write anytime except when eepgm = 1 or eediv = 0. byte, row, erase and eelat bits can be wr itten simultaneously or in any sequence. eepgm ? program and erase enable 0 = disables program/era se voltage to eeprom. 1 = applies program/era se voltage to eeprom. the eepgm bit can be set only afte r eelat has b een set. when eelat and eepgm are set simult aneously, eepgm remains clear but eelat is set. the bulkp, auto, byte, row, erase and eelat bits cannot be changed when eepgm is se t. to complete a pr ogram or erase cycle when auto bit is cl ear, two successive writ es to clear eepgm and eelat bits are required before reading the prog rammed data. when the auto bit is set, eepgm is automatically cleared after the program or erase cycle completes. note that if an attempt is made to modify a protected block location t he modify cycle do es not start and the eepgm bit isn?t automatically cleared. a write to an eeprom location has no effect when eepgm is set. latched address and data cannot be modified during program or erase.
eeprom memory program/erase operation mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor eeprom memory 115 8.6 program/erase operation a program or erase oper ation should follow the sequence below if auto bit is clear: 1. write byte, row and erase to desired value, write eelat = 1 2. write a byte or an aligned word to an eeprom address 3. write eepgm = 1 4. wait for programming, t prog or erase, t erase delay time (10ms) 5. write eepgm = 0 6. write eelat = 0 if the auto bit is set, steps 4 and 5 can be replaced by a step to poll the eepgm bit until it is cleared. it is possible to program/erase more bytes or words without intermediate eeprom reads, by jumping from step 5 to step 2. 8.7 shadow word mapping the shadow word is mapped to lo cation $_fc0 and $_fc1 when the noshw bit in eemcr register is ze ro. the value in th e shadow word is loaded to the eemc r, eedivh and eedivl after reset. table 8-4 shows the mapping of each bit from shadow word to the registers table 8-4. shadow word mapping shadow word location register / bit $_fc0 bit 7 eemcr / nobdml $_fc0, bit 6 eemcr / noshw $_fc0, bit 5 eemcr / bit 5 (1) 1. reserved for testing. must be set to one in user application. $_fc0, bit 4 eemcr / fpopen $_fc0, bit 3:2 not mapped (2) 2. reserved. must be set to one in user application for future compatibility. $_fc0, bit 1:0 eedivh / bit 1:0 $_fc1, bit 7:0 eedivclk / bit 7:0
eeprom memory technical data mc68hc9 12d60a ? rev. 3.1 116 eeprom memory free scale semiconductor 8.8 programming eedivh and eedivl registers the eedivh and eedivl regi sters must be correctly set according to the oscillator frequency before any eeprom location can be programmed or erased. 8.8.1 normal mode the eedivh and eedivl regi sters are writ e once in normal mode. upon system reset, the application program is required to write the correct divider value to eedivh and eedivl registers based on the oscillator frequency. af ter the first write, th e value in the eedivh and eedivl registers is lo cked from being overwritt en until the next reset. the eeprom is then ready for st andard program/erase routines. caution: runaway code can possibly corrupt the eedivh and eed ivl registers if they are not initia lized for the write once. 8.8.2 special mode if an existing applicat ion code with eepr om program/erase routines is already fixed and the system is already operating at a known oscillator frequency, it is recommended to in itialize the shadow word with the corresponding eedivh and eedivl values in special mode. the shadow word initialize s eedivh and eedivl registers upon system reset to ensure software compatibility with existi ng code. initializing the eedivh and eedivl regi sters in special modes (smodn=0) is accomplished by t he following steps. 1. write correct divider value to eedivh and eedi vl registers based on the oscillator frequency as per table17. 2. remove the shadow word protec tion by clearing shprot bit in eeprot register. 3. clear noshw bit in eemcr regist er to make the shadow word visible at $0fc0-$0fc1. 4. program bits 1 and 0 of the high byte of the shadow word and bits 7 to 0 of the lo w byte of the shadow word like a regular
eeprom memory programming eedivh and eedivl registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor eeprom memory 117 eeprom location at address $0fc 0 and $0fc1. do not program other bits of the high byte of th e shadow word (location $0fc0); otherwise some regul ar eeprom array loca tions will not be visible. at the next reset, the s hadow values are loaded into the eedivh and eedivl r egisters. they do not require further initialization as long as the osc illator frequency of the target application is not changed. 5. protect the shadow word by setting shprot bit in eeprot register.
eeprom memory technical data mc68hc9 12d60a ? rev. 3.1 118 eeprom memory free scale semiconductor
mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor resets and interrupts 119 technical data ? mc68hc912d60a section 9. resets and interrupts 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 9.3 maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 9.4 latching of interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.5 interrupt control and priority regist ers . . . . . . . . . . . . . . . . . 123 9.6 resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.7 effects of reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9.8 register stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.9 customer information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 9.2 introduction cpu12 exceptions include resets and interrupts. each exception has an associated 16-bit vector, which points to the memory location where the routine that handles the e xception is located. ve ctors are stored in the upper 128 bytes of the standar d 64k byte address map. the six highest vector addresses are used for resets and non-maskable interrupt sources. the remainder of the vectors are used for maskable interrupts, and all must be initiali zed to point to the address of the appropriate service routine. 9.2.1 exception priority a hardware priority hier archy determines which reset or interrupt is serviced first when simult aneous requests are made. six sources are not
resets and interrupts technical data mc68hc9 12d60a ? rev. 3.1 120 resets and interrupts freescale semiconductor maskable. the remaining sources are maskable, and any one of them can be given priority over other maskable interrupts. the priorities of the n on-maskable sources are: 1. por or reset pin 2. clock monitor reset 3. cop watchdog reset 4. unimplemented instruction trap 5. software interrupt instruction (swi) 6. xirq signal (if x bit in ccr = 0) 9.3 maskable interrupts maskable interrupt sources in clude on-chip peripheral systems and external interrupt service requests. interrupts from these sources are recognized when the global interrupt mask bit (i) in the ccr is cleared. the default state of the i bi t out of reset is one, but it can be written at any time. interrupt sources are prioritized by default but any one maskable interrupt source may be assigned the highest priori ty by means of the hprio register. the relati ve priorities of the ot her sources remain the same. an interrupt that is assigned highest pr iority is still subject to global masking by the i bit in the ccr, or by any associated local bits. interrupt vectors are not affect ed by priority assignm ent. hprio can only be written while the i bit is set (interrupts inhibited). table 9-1 lists interrupt sources and vectors in de fault order of priority.
resets and interrupts latching of interrupts mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor resets and interrupts 121 9.4 latching of interrupts xirq is always level triggered and irq can be selected as a level triggered interrupt. these level tri ggered interrupt pins should only be released during the appropriate interrupt service routine. generally the interrupt service routi ne will handshake with the interrupting logic to release the pin. in this way, the mcu will sta rt the interrupt service sequence only to determine that there is no longer an interrupt source. in the event that this does not occur, the trap vector will be taken. if irq is selected as an edge triggered inte rrupt, the hold time of the level after the active edge is independent of when the interrupt is serviced. as long as the minimum hold time is met, the interrupt will be latched inside the mcu. in this ca se the irq edge interrupt latch is cleared automatically when the interrupt is serviced. all of the remaining in terrupts are latched by t he mcu with a flag bit. these interrupt flags should be cl eared during an interrupt service routine or when interr upts are masked by the i bit. by doing this, the mcu will never get an unknown interrupt source and take the trap vector.
resets and interrupts technical data mc68hc9 12d60a ? rev. 3.1 122 resets and interrupts freescale semiconductor table 9-1. interrupt vector map vector address interrupt source ccr mask local enable hprio value to elevate $fffe, $ffff reset none none ? $fffc, $fffd clock monitor fail reset none copctl (cme, fcme) ? $fffa, $fffb cop failure reset none cop rate selected ? $fff8, $fff9 unimplemented instruction trap none none ? $fff6, $fff7 swi none none ? $fff4, $fff5 xirq x bit none ? $fff2, $fff3 irq i bit intcr (irqen) $f2 $fff0, $fff1 real time interrupt i bit rtictl (rtie) $f0 $ffee, $ffef timer channel 0 i bit tmsk1 (c0i) $ee $ffec, $ffed timer channel 1 i bit tmsk1 (c1i) $ec $ffea, $ffeb timer channel 2 i bit tmsk1 (c2i) $ea $ffe8, $ffe9 timer channel 3 i bit tmsk1 (c3i) $e8 $ffe6, $ffe7 timer channel 4 i bit tmsk1 (c4i) $e6 $ffe4, $ffe5 timer channel 5 i bit tmsk1 (c5i) $e4 $ffe2, $ffe3 timer channel 6 i bit tmsk1 (c6i) $e2 $ffe0, $ffe1 timer channel 7 i bit tmsk1 (c7i) $e0 $ffde, $ffdf timer overflow i bit tmsk2 (toi) $de $ffdc, $ffdd pulse accumulator overflow i bit pactl (paovi) $dc $ffda, $ffdb pulse accumulator input edge i bit pactl (pai) $da $ffd8, $ffd9 spi serial transfer complete i bit sp0cr1 (spie) $d8 $ffd6, $ffd7 sci 0 i bit sc0cr2 (tie, tcie, rie, ilie) $d6 $ffd4, $ffd5 sci 1 i bit sc1cr2 (tie, tcie, rie, ilie) $d4 $ffd2, $ffd3 atd0 or atd1 i bit atdxctl2 (ascie) $d2 $ffd0, $ffd1 mscan wake-up i bit crier (wupie) $d0 $ffce, $ffcf key wake-up g or h i bit kwieg[6:0] and kwieh[7:0] $ce $ffcc, $ffcd modulus down counter underflow i bit mcctl (mczi) $cc $ffca, $ffcb pulse accumulator b overflow i bit pbctl (pbovi) $ca $ffc8, $ffc9 mscan errors i bit crier (rwrnie, twrnie, rerrie, terrie, boffie, ovrie) $c8 $ffc6, $ffc7 mscan receive i bit crier (rxfie) $c6 $ffc4, $ffc5 mscan transmit i bit ctcr (txeie[2:0]) $c4 $ffc2, $ffc3 cgm lock and limp home i bit pllcr (lockie, lhie) $c2 $ff80?$ffc1 reserved i bit $80?$c0
resets and interrupts interrupt control and priority registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor resets and interrupts 123 9.5 interrupt control and priority registers irqe ? irq select edge sensitive only 0 = irq configured for low-level recognition. 1 = irq configured to respond only to falling edges (on pin pe1/irq ). irqe can be read anyt ime and written once in normal modes. in special modes, irqe can be read anytime and written anytime, except the first write is ignored. irqen ? external irq enable the irq pin has an active pull-up. see table 3-4 . 0 = external irq pin is disconnected from interrupt logic. 1 = external irq pin is connected to interrupt logic. irqen can be read and written anytime in all modes. dly ? enable oscillator start- up delay on exit from stop the delay time of about 4096 cycles is based on the x clock rate chosen. 0 = no stabilization delay impos ed on exit from stop mode. a stable external oscill ator must be supplied. 1 = stabilization delay is imposed before processing resumes after stop. dly can be read anytime and writte n once in normal modes. in special modes, dly can be r ead and written anytime. bit 7654321bit 0 irqe irqen dly 0 0 0 0 0 reset: 0 1 1 0 0 0 0 0 intcr ? interrupt control register $001e
resets and interrupts technical data mc68hc9 12d60a ? rev. 3.1 124 resets and interrupts freescale semiconductor write only if i mask in ccr = 1 (int errupts inhibited) . read anytime. to give a maskable interrupt source highest priority, write the low byte of the vector address to the hprio regi ster. for example, writing $f0 to hprio would assign highest maskable interrupt prio rity to the real-time interrupt timer ($fff0). if an un-imple mented vector address or a non-i- masked vector address (value higher than $f2) is writ ten, then irq will be the default highest priority interrupt. 9.6 resets there are four possible sources of reset. power-on reset (por), and external reset on the reset pin share the normal reset vector. the computer operating prop erly (cop) reset and the clock monitor reset each has a vector. entry into reset is asynchronous and does not require a clock but the mcu cannot sequenc e out of reset without a system clock. 9.6.1 powe r-on reset a positive transition on v dd causes a power-on reset (por). an external voltage level detector, or other external reset circuits, are the usual source of reset in a system. the por circuit only initia lizes internal circuitry during cold starts and cannot be used to force a reset as system voltage drops. it is important to use an external low voltage rese t circuit (for example: mc34064 or mc33464) to pr event power transitions or corruption of ram or eeprom. bit 7654321bit 0 1 1 psel5 psel4 psel3 psel2 psel1 0 reset: 1 1 1 1 0 0 1 0 hprio ? highest priority i interrupt $001f
resets and interrupts resets mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor resets and interrupts 125 9.6.2 external reset the cpu distinguishes be tween internal and exter nal reset conditions by sensing whether the reset pin rise s to a logic one in less than eight eclk cycles after an internal dev ice releases reset. when a reset condition is sensed, the reset pin is driven low by an internal device for about 16 eclk cycles, then released . eight eclk cycles later it is sampled. if the pin is st ill held low, t he cpu assumes that an external reset has occurred. if the pin is high, it indica tes that the reset was initiated internally by either the cop system or the clock monitor. to prevent a cop or cloc k monitor reset from be ing detected during an external reset, hold the reset pin low for at least 32 cycles. an external rc power-up delay circuit on the reset pin is not recommended as circuit charge time can cause the mcu to misint erpret the type of reset that has occurred. 9.6.3 cop reset the mcu includes a comput er operating properly (cop) system to help protect against software failures. w hen cop is enabled , software must write $55 and $aa (in this order) to t he coprst register in order to keep a watchdog timer from timing out. other instructions may be executed between these writes. a write of any value other than $55 or $aa or software failing to execute the sequenc e properly causes a cop reset to occur. in addition, wi ndowed cop operation can be selected. in this mode, a write to the copr st register must occur in the last 25% of the selected period. a premature wr ite will also reset the part. 9.6.4 clock monitor reset if clock frequency falls below a predetermined limit when the clock monitor is enabled, a reset occurs.
resets and interrupts technical data mc68hc9 12d60a ? rev. 3.1 126 resets and interrupts freescale semiconductor 9.7 effects of reset when a reset occurs, mcu register s and control bits are changed to known start-up states, as follows. 9.7.1 operating mode and memory map operating mode and default memory mapping are determined by the states of the bkgd, moda, and modb pins during rese t. the smodn, moda, and modb bits in th e mode register reflec t the status of the mode-select inputs at the rising edge of reset. operating mode and default maps can subsequently be c hanged according to strictly defined rules. 9.7.2 clock and wa tchdog control logic the cop watchdog system is enabled, with the cr[2:0 ] bits set for the longest duration time-out . the clock monitor is disabled. the rtif flag is cleared and automatic hardware interrupts are masked. the rate control bits are cleared, and must be initialized before the rti system is used. the dly control bit is set to specify an osci llator start-up delay upon recovery from stop mode. 9.7.3 interrupts psel is initialized in t he hprio register with t he value $f2, causing the external irq pin to have the highest i-bit interrupt priority. the irq pin is configured for level-sensitive operation (for wired-or systems). however, the interrupt mask bits in the cpu12 ccr are set to mask x- and i-related interrupt requests. 9.7.4 parallel i/o if the mcu comes out of reset in a single-chip mode, all ports are configured as general- purpose high-impedance inputs.
resets and interrupts register stacking mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor resets and interrupts 127 if the mcu comes out of reset in an expanded mode, port a and port b are used for the address/data bus, and por t e pins are normally used to control the external bus (operation of port e pins can be affected by the pear register). out of reset, port g, port h, port p, po rt s, port t, port can[7:2], port ad0 and port ad1 are all conf igured as general-purpose inputs. 9.7.5 central processing unit after reset, the cpu fetc hes a vector from the appropriate address, then begins executing instructions. the st ack pointer and other cpu registers are indeterminate immediately afte r reset. the ccr x and i interrupt mask bits are set to mask any interrup t requests. the s bit is also set to inhibit the stop instruction. 9.7.6 memory after reset, the internal register block is located from $0000 to $01ff, ram is at $0000 to $07f f, and eeprom is loca ted at $0c00 to $0fff. in single chip mode the two flas h eeprom modules ar e located from $1000 to $7fff and $8000 to $ffff. 9.7.7 other resources the enhanced capture timer (ect), pulse width modulation timer (pwm), serial communications inte rfaces (sci0 and sci1), serial peripheral interface (spi ), scalable can (mscan) and analog-to-digital converters (atd0 and atd1) are off after reset. 9.8 register stacking once enabled, an interrupt request can be re cognized at any time after the i bit in the ccr is cleared. wh en an interrupt service request is recognized, the cpu respon ds at the completion of the instruction being executed. interrupt latency varies according to the number of cycles
resets and interrupts technical data mc68hc9 12d60a ? rev. 3.1 128 resets and interrupts freescale semiconductor required to complete the in struction. some of the longer instructions can be interrupted and will resume normall y after servicing the interrupt. when the cpu begins to service an in terrupt, the instruction queue is cleared, the return address is calcul ated, and then it and the contents of the cpu register s are stacked as shown in table 9-2 . after the ccr is stacked, the i bit (and the x bit, if an xirq interrupt service request is pending) is set to prevent other interrupts from disrupting the interrupt service routine. the interrupt vector for the highest priority source that was pending at the begi nning of the interrupt sequence is fetched, and ex ecution continues at th e referenced location. at the end of the interrup t service routine, an rti instruction restores the content of all re gisters from information on the stack, and normal program execution resumes. if another interrupt is pendi ng at the end of an inte rrupt service routine, the register unstacking and restacking is bypassed an d the vector of the interrupt is fetched. 9.9 customer information before disabling an interr upt using a local interrup t control bit, set the i mask bit in the ccr. failing to do so may caus e an swi interrupt to be fetched instead of the vector for the interrup t source that was disabled. table 9-2. stacking order on entry to interrupts memory location cpu registers sp ? 2 rtn h : rtn l sp ? 4 y h : y l sp ? 6 x h : x l sp ? 8 b : a sp ? 9 ccr
mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor i/o ports with key wake-up 129 technical data ? mc68hc912d60a section 10. i/o ports with key wake-up 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 10.3 key wake-up and port r egisters . . . . . . . . . . . . . . . . . . . . . . 130 10.4 key wake-up input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 10.2 introduction the 112qfp mc68hc912d60a offers 16 additional i/o po rt pins with key wake-up capability on 15 of them (kwg7 is used for i 2 c start detect). only two (kwg4 and kw h4) are availabl e on the 80qfp package. all port g and port h pins should either be defined as outputs or have their pull-ups/downs enabled. the key wake-up feature of the mc 68hc912d60a issues an interrupt that will wake up the cpu when it is in the stop or wait mode. two ports are associated with the key wake-up function: port g and port h. port g and port h wake-ups are trigger ed with a falling signal edge. for each pin which has an interr upt enabled, there is a path to the interrupt request signal which ha s no clocked devices w hen the part is in stop mode. this allows an active edge to bring the part out of stop. digital filtering is in cluded to prevent pulses shorter than a specified value from waking the part from stop. an interrupt is generated when a bit in the kwifg or kwifh register and its corresponding kwieg or kwieh bi t are both set. all 15 bits/pins share the same interrupt vector. key wake-ups can be used with the pins configured as inputs or outputs.
i/o ports with key wake-up technical data mc68hc9 12d60a ? rev. 3.1 130 i/o ports with key wake-up freescale semiconductor pull-up/down status is selected by pgupd and phupd input pins: pull- up when pxupd pin is high, pull-dow n when pxupd pin is low. on 80qfp these pins are tied internally so that kwg4 is pull-up and kwh4 is pull-down. default register addresses, as estab lished after reset, are indicated in the following descriptions. for inform ation on re-mapping the register block, refer to operating modes and resource mapping . 10.3 key wake-up and port registers read and write anytime. read and write anytime. bit 7654321bit 0 pg7 pg6 pg5 pg4 pg3 pg2 pg1 pg0 reset:???????? alt. pin function ? kwg6 kwg5 kwg4 kwg3 kwg2 kwg1 kwg0 portg ? port g register $0028 bit 7654321bit 0 ph7 ph6 ph5 ph4 ph3 ph2 ph1 ph0 reset: ? ? ? ? ? ? ? ? alt. pin function kwh7 kwh6 kwh5 kwh4 kwh3 kwh2 kwh1 kwh0 porth ? port h register $0029
i/o ports with key wake-up key wake-up and port registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor i/o ports with key wake-up 131 data direction register g is asso ciated with port g and designates each pin as an input or output. read and write anytime 0 = associated pin is an input 1 = associated pin is an output data direction register h is associated with port h and designates each pin as an input or output. read and write anytime. 0 = associated pin is an input 1 = associated pin is an output bit 7654321bit 0 ddg7 ddg6 ddg5 ddg4 ddg3 ddg2 ddg1 ddg0 reset: 0 0 0 0 0 0 0 0 ddrg ? port g data direction register $002a bit 7654321bit 0 ddh7 ddh6 ddh5 ddh4 ddh3 ddh2 ddh1 ddh0 reset: 0 0 0 0 0 0 0 0 ddrh ? port h data direction register $002b
i/o ports with key wake-up technical data mc68hc9 12d60a ? rev. 3.1 132 i/o ports with key wake-up freescale semiconductor read and write anytime. wi2ce ? wake-up i 2 c enable 0 = pg6 default key wa ke-up on falling edge 1 = i 2 c start condition detec tion on pg7 and pg6 when wi2ce is set, pg6 and pg7 oper ate in wired-or or open-drain mode. the i 2 c start condition is defined as a high to low transition of the sda line when scl is high. when wi 2ce is set, a falling edge on pg6 (sda) is recognized on ly if pg7 (scl) is high. depending on wi2ce bit, kwieg6 enables either falling edge or i 2 c start condition interrupt. kwieg[6:0] ? key wake-up port g interrupt enables 0 = interrupt for the associated bit is disabled 1 = interrupt for the a ssociated bit is enabled read and write anytime. kwieh[7:0] ? key wake-up port h interrupt enables 0 = interrupt for the associated bit is disabled 1 = interrupt for the a ssociated bit is enabled bit 7654321bit 0 wi2ce kwieg6 kwieg5 kwieg4 k wieg3 kwieg2 kwieg1 kwieg0 reset:00000000 kwieg ? key wake-up port g interrupt enable register $002c bit 7654321bit 0 kwieh7 kwieh6 kwieh5 kwieh4 kwieh3 kwieh2 kwieh1 kwieh0 reset: 0 0 0 0 0 0 0 0 kwieh ? key wake-up port h interrupt enable register $002d
i/o ports with key wake-up key wake-up and port registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor i/o ports with key wake-up 133 each flag, except bit 6, is set by a falling edge on its a ssociated input pin. to clear the flag, wr ite one to the corres ponding bit in kwifg. read and write anytime bit 7 always reads zero. kwifg6 ? key wake-up port g flag 6 0 = falling edge on the associated bit or i2c start condition has not occurred 1 = falling edge on the associated bit or i2c start condition has occurred (an interrupt will occur if the associ ated enable bit is set) depending on wi2ce bit in kwieg register, kwifg6 flags either falling edge or i2c start condition. kwifg[5:0] ? key wa ke-up port g flags 0 = falling edge on the associated bit has not occurred 1 = falling edge on the associated bit has occurred (an interrupt will occur if the associat ed enable bit is set). bit 7654321bit 0 0 kwifg6 kwifg5 kwifg4 kwifg3 kwifg2 kwifg1 kwifg0 reset:00000000 kwifg ? key wake-up port g flag register $002e
i/o ports with key wake-up technical data mc68hc9 12d60a ? rev. 3.1 134 i/o ports with key wake-up freescale semiconductor read and write anytime. each flag is set by a falling edge on it s associated input pin. to clear the flag, write one to the corresponding bit in kwifh. kwifh[7:0] ? key wa ke-up port h flags 0 = falling edge on the associated bit has not occurred 1 = falling edge on the associated bit has occurred (an interrupt will occur if the associ ated enable bit is set) 10.4 key wake-up input filter the kwu input signals are fi ltered by a digital filt er which is active only during stop mode. the purpose of the fi lter is to prevent single pulses shorter than a specified value from waking the part from stop. the filter is composed of an internal o scillator and a majority voting logic. the filter oscillator starts the oscillat ion by detecting a triggering edge on an input if the correspond ing interrupt enable bit is set. the majority voting logic takes three samples of an asserted input pin at each filter oscillator period and if two samples ar e taken at the tri ggering leve l, the filter recognizes a va lid triggering level and sets the corresponding interrupt flag. in this way the majo rity voting logic re jects the short non- triggering state between tw o incoming triggering puls es. as the filter is shared with all kwu inputs , the filter considers any pulse coming from any input pin for which the corres ponding interrupt enable bit is set. the timing specification is given for a single pulse. the time interval between the triggering edges of two following pu lses should be greater than the t kwsp in order to be consi dered as a single pulse by the filter. if bit 7654321bit 0 kwifh7 kwifh6 kwifh5 kwifh4 kwifh3 kwifh2 kwifh1 kwifh0 reset: 00000000 kwifh ? key wake-up port h flag register $002f
i/o ports with key wake-up key wake-up input filter mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor i/o ports with key wake-up 135 this time interval is shorter than t kwsp , the majority voting logic may treat the two consecutive pulses as a single valid pulse. the filter is shared by al l the kwu pins. hence any valid triggering level on any kwu pin is seen by the filter . the timing specif ication applies to the input of the filter. figure 10-1. stop key wake-up filter (falling edge trigger) timing glitch, filtered out, no stop wake-up valid stop wake-up pulse t kwstp min. t kwsp minimum time interval between pulses to be recognized as single pulses t kwstp max.
i/o ports with key wake-up technical data mc68hc9 12d60a ? rev. 3.1 136 i/o ports with key wake-up freescale semiconductor
mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor clock functions 137 technical data ? mc68hc912d60a section 11. clock functions 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 11.3 clock sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 11.4 phase-locked loop (p ll) . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 11.5 acquisition and tracking modes. . . . . . . . . . . . . . . . . . . . . . . 141 11.6 limp-home and fast stop recove ry modes . . . . . . . . . . . . 143 11.7 system clock frequency formulas . . . . . . . . . . . . . . . . . . . . . 162 11.8 clock divider chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 11.9 computer operating prop erly (cop) . . . . . . . . . . . . . . . . . . . 166 11.10 real-time interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 11.11 clock monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167 11.12 clock function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 11.2 introduction clock generation ci rcuitry generates the inte rnal and external eclk signals as well as internal clock signals used by th e cpu and on-chip peripherals. a clock monitor circui t, a computer ope rating properly (cop) watchdog circuit, and a periodi c interrupt circuit are also incorporated into the mc68hc912d60a.
clock functions technical data mc68hc9 12d60a ? rev. 3.1 138 clock functions freescale semiconductor 11.3 clock sources a compatible external clock signal can be applied to the extal pin or the mcu can generate a clo ck signal using an on-chip oscillator circuit and an external crystal or ceramic resonator. the mcu uses several types of internal clock signals deriv ed from the primary clock signal: txclk clocks are used by the cpu. eclk and pclk are used by the bus interfaces, spi, pwm, atd0 and atd1. mclk is either pclk or xclk, a nd drives on-chip modules such as sci0, sci1 and ect. xclk drives on-chip m odules such as rti, co p and restart-from-stop delay time. slwclk is used as a calibration output signal. the mscan module is clocked by ext ali or sysclk, u nder control of an mscan bit. the clock monitor is clocked by extali. the bdm system is clocked by bclk or eclk, under control of a bdm bit. a slow mode clock divider is inclu ded to deliver a lower clock frequency for the sci baud rate gener ators, the ect timer module, and the rti and cop clocks. the slow clock bus frequ encies divide the crystal frequency in a programmable range of 4 to 252, with steps of 4. figure 11-1 shows some of the timi ng relationships. see the clock divider chains section for further details.
clock functions phase-locked loop (pll) mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor clock functions 139 figure 11-1. internal clock relationships 11.4 phase-locked loop (pll) the phase-locked loop (pll) of the mc68hc912d 60a is designed for robust operation in an au tomotive environment. the allowed pll crystal or ceramic resonator reference of 0. 5 to 8mhz is selected for the wide availability of compo nents with good stability over the automotive temperature range. please refer to figure 11-6 in section clock divider chains for an overview of system clocks. note: when selecting a crystal, it is re commended to use one wi th the lowest possible frequency in order to minimise emc emissions. an oscillator design wit h reduced power consumpt ion allows for slow wait operation with a typical power supply current less than a milli- ampere. the pll circuitry can be by passed when the vddpll supply is at vss level. in this case, the pll module is powered down and the oscillator output transistor has a st ronger transconduct ance for improved drive of higher frequency resonators (as the cr ystal frequency needs to be twice the maximum bus frequency). refer to figure 3-5 in pinout and signal descriptions . t1clk t2clk t3clk t4clk int eclk pclk xclk canclk
clock functions technical data mc68hc9 12d60a ? rev. 3.1 140 clock functions freescale semiconductor figure 11-2. pll functional diagram the pll may be used to run the mcu fr om a different time base than the incoming crystal value. it creates an integer multiple of a reference frequency. for increased flexibility, the crystal clock can be divided by values in a range of 1 ? 8 (in uni t steps) to generate the reference frequency. the pll can multiply this reference clock in a range of 1 to 64. although it is possible to set the divider to command a very high clock frequency, do not exceed the specified bus freque ncy limit for the mcu. if the pll is selected, it will cont inue to run when in wait mode resulting in more power consumpt ion than normal. to take full advantage of the reduced power consumption of wait mode, turn off the pll before going into wait. pleas e note that in this case the pll stabilization time applies. the pll operation is suspended in stop mode. after stop exit followed by the st abilization time, it resumes operati on at the same frequency, provided t he auto bit is set. a passive external loop filter must be placed on the control line (xfc pad). the filter is a sec ond-order, low-pass filter to eliminat e the vco input ripple. values of compo nents in the diagr am are dependent upon the desired vco operation. see xfc description. reduced consumption oscillator extal xtal extali pllclk reference programmable divider pdet phase detector refdv <2:0> loop programmable divider syn <5:0> cpump vco lock loop filter xfc pad up down lock detector refclk divclk slow mode programmable clock divider sldv <5:0> xclk extali 2 slwclk vddpll 2
clock functions acquisition and tracking modes mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor clock functions 141 11.5 acquisition and tracking modes the lock detector compares the freque ncies of the vco feedback clock, divclk, and the final reference clo ck, refclk. theref ore, the speed of the lock detector is directly proportional to the final reference frequency. the circuit determines the mode of the pll and the lock condition based on this comparison. the pll filter is manually or automatically conf igurable into one of two operating modes: acquisition mode ? in acquisition m ode, the filter can make large frequency corrections to the vco. this mode is used at pll start- up or when the pll has suffered a severe noise hit and the vco frequency is far off the desired frequency. this mode can also be desired in harsh environments when the leakage levels on the filter pin (xfc) can overcome the tracking currents of the pll charge pump. when in ac quisition mode, the acq bit in the pll control register is clear. tracking mode ? in tracking mode , the filter makes only small corrections to the frequency of the vco. the pll enters tracking mode when the vco fr equency is nearly co rrect. the pll is automatically in tracking mode wh en not in acqui sition mode or when the acq bit is set. the pll can change the bandwidth or oper ational mode of the loop filter manually or automatically. with an i dentical filtering ti me constant, the pll bandwidth is larger in acquisition mode than in tracking by a ratio of about 3. in automatic bandwidth control mode (auto = 1), the lock detector automatically switches between acquisition and tracking modes. automatic bandwidth c ontrol mode also is us ed to determi ne when the vco clock, pllclk, is sa fe to use as the source for the base clock, sysclk. if pll lock interrupt r equests are enabled, the software can wait for an interrupt request and then check the lock bit. if cpu interrupts are disabled, software can poll the lock bit continuously (during pll start-up, usually) or at periodic intervals. in either case, when the lock bit is set, the pllclk clock is safe to use as the source
clock functions technical data mc68hc9 12d60a ? rev. 3.1 142 clock functions freescale semiconductor for the base clock. see clock divider chains . if the vco is selected as the source for the base clock and t he lock bit is clear, the pll has suffered a severe noise hit and the software mu st take appropriate action, depending on the application. the following conditions apply when t he pll is in automatic bandwidth control mode: the acq bit is a read-only indicato r of the mode of the filter. the acq bit is set when the vco fr equency is within a certain tolerance, ? trk , and is cleared when the vco frequency is out of a certain tolerance, ? unt . see 19 electrical characteristics. the lock bit is a read-only indicator of the locked state of the pll. the lock bit is set when the vco frequency is within a certain tolerance, ? lock , and is cleared when the vco frequency is out of a certain tolerance, ? unl . see 19 electrical characteristics. cpu interrupts can occur if enabled (lockie = 1) when the lock condition changes, toggl ing the lock bit. the pll also can operate in manual mode (auto = 0). all lock features described above are active in this mode, onl y the bandwidth control is disabled. manual mode is used mainly for systems operating under harsh conditions (e.g. uncoated pcbs in automotive environments). when this is the case, the pll is likely to remain in acquisition mode. the fo llowing conditions appl y when in manual mode: acq is a writable control bit that controls t he mode of the filter. before turning on the pll in manual mode, the acq bit must be clear. in case tracking is desired (acq = 1), the software must wait a given time, tacq, after turning on the pll by setting pllon in the pll control register. this is to avoid switching to tracking mode too early while t he xfc voltage level is stil l too far away from its quiescent value corresponding to the target frequency. this operation would be very detriment al to the stabi lization time.
clock functions limp-home and fast stop recovery modes mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor clock functions 143 11.6 limp-home and fast stop recovery modes if the crystal frequency is not available due to a crystal failure or a long crystal start-up time, the mcu system clock can be supplied by the vco at its minimum oper ating frequency, f vcomin . this mode of operation is called limp-home mode and is only available when the vddpll supply voltage is at vdd level (i.e. power su pply for the pll module is present). upon power-up, the abilit y of the system to star t in limp-home mode is restricted to norma l mcu modes only. the clock monitor circuit (see section clock monitor) can detect the loss of extali, the external clock input signal, regardless of whether this signal is used as the so urce for mcu clocks or as the pll reference clock. the clock monitor contro l bits, cme and fcme, are used to enable or disable exter nal clock detection. a missing external clock may occur in the three following instances: during normal clock operation. at power-on reset. in the stop exit sequence 11.6.1 clock loss during normal operation the ?no limp-home mode ? bit, nolhm, deter mines how the mcu responds to an external cl ock loss in this case. with limp home mode disabled (n olhm bit set) and the clock monitor enabled (cme or fcme bits set), on a loss of clo ck the mcu is reset via the clock monitor reset vector. a latc h in the pll contro l section prevents the chip exiting reset in limp home mode (this is required as the nolhm bit gets cleared by reset). only exter nal clock activity can bring the mcu out from this reset state. once rese t has been exited, th e latch is cleared and another session, with or without limp home mode enabled, can take place. this is t he same behavior as stan dard m68hc12 circuits without pll or ope ration with vddpll at vss level. with limp home mode enabled (n olhm bit cleared) and the clock monitor enabled (cme or fc me bits set), on a lo ss of clock, the pll
clock functions technical data mc68hc9 12d60a ? rev. 3.1 144 clock functions freescale semiconductor vco clock at its mi nimum frequency, f vcomin , is provided as the system clock, allowing the mc u to continue operating. the mcu is said to be operating in ?limp-home? mode with the forced vco clock as the system clock. pllon and bcsp (?bus clock select pll?) signals are forced high and the mcs (?module clock select?) signal is forced low. the lhome flag in the pllflg register is set to indicate that the mcu is running in limp-home mode. a change of this flag sets the limp-home interrupt flag, lhif, and if enabled by t he lhie bit, the limp-home mode interrupt is requ ested. the clock monitor is enabled irrespective of cme and fcme bit se ttings. module clocks to the rti & cop (xclk), bdm (bclk) and ect & sci (mclk) are forced to be pclk (at f vcomin ) and eclk is also equal to f vcomin . mscan clock select is unaffected. figure 11-3. clock loss durin g normal operation the clock monitor is polled each ti me the 13-stage free running counter reaches a count of 4096 xclk cycles i.e. mi d-count, hence the clock status gets checked once every 8192 xclk cycles. when the presence of an external clock is detected, the mcu exits limp-home mode, clearing the lhome flag and setting t he limp-home interr upt flag. upon leaving limp-home mode, bcsp and mcs si gnals are restored to their 0 --> 4096 limp-home (clocked by xclk) bcsp restore bcsp sysclk pllclk (limp-home) restore pllclk or extali extali 13-stage counter clock monitor fail 0 --> 4096 ab
clock functions limp-home and fast stop recovery modes mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor clock functions 145 values before the clock loss. all clocks return to their normal settings and clock monitor control is returned to the cme & fcme bits. if auto and bcsp bits were set before the clock loss (selecting the pll to provide a system clock) the sysclk ramps-up and the pll locks at the previously selected frequency. to prevent pll oper ation when the external clock frequency comes back, soft ware should clear the bcsp bit while running in limp-home mode. the two shaded regions a and b in figure 11-3 present a of code run away due to incorrect clocks on sy sclk if the mcu is clocked by extali and the p ll is not used. in region a , there is a delay between the loss of clock and its detection by the clock monitor. when the ext ali clock signal is disturbed, the clock generation circuitry may receive an out of spec signal and drive the cpu with irregular clocks. th is may lead to code runaway. in region b , as the 13-stage coun ter is free running, the count of 4096 may be reached when the amplitude of the exta li clock has not stabilized. in this case, an impr oper extali is sent to the clock generation circuitry when limp-home mode is exited . this may also cause code runaway. if the mcu is clocked by the pll, the risk of code runaway is very low, but it c an still occur under certain conditions due to irregular clocks from the clock sour ce appearing on the sysclk. caution: the cop watch dog should always be enabled in orde r to reset the mcu in case of a code runaway situation. note: it is always advisable to take additional precautions within the application software to trap such situations. 11.6.2 no clock at power-on reset the voltage level on v ddpll determines how t he mcu responds to an external clock loss in this case. with the vddpll supply vo ltage at vdd level, any reset sets the clock monitor enable bit (cme ) and the pllon bit and clears the nolhm bit.
clock functions technical data mc68hc9 12d60a ? rev. 3.1 146 clock functions freescale semiconductor therefore, if the mcu is powered up without an external clock, limp- home mode is entered pr ovided the mcu is in a normal mode of operation. figure 11-4. no clock at power-on reset vdd power-on detector clock monitor fail extali 13-stage counter internal reset 0 --> 4096 limp-home (clocked by xclk) bcsp reset: bcsp = 0 sysclk pllclk (l.h.) extali sysclk pllclk (software check of limp-home flag) extali (slow extali) 0 --> 4096 (slow extali)
clock functions limp-home and fast stop recovery modes mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor clock functions 147 during this power up sequence, afte r the por pulse fa lling edge, the vco supplies the limp-hom e clock frequency to t he 13-stage counter, as the bcsp output is forced high and mcs is forced low. xclk, bclk and mclk are forced to be pclk, which is supplied by the vco at f vcomin . the initial period taken for the 13-st age counter to reach 4096 defines the internal reset period. if the clock monitor indi cates the presence of an external clock during the internal reset period, limp-home mode is de-asserted and the 13-stage counter is then driven by extali clock. afte r the 13-stage counter reaches a count of 4096 xclk cycles, t he internal reset is released, the 13-stage counter is reset and t he mcu exits reset normally using extali clock. however, if the crystal start-up time is longer than the initial count of 4096 xclk cycles, or in the absence of an exter nal clock, the mcu will leave the reset state in limp-hom e mode. the lhom e flag is set and lhif limp-home interrupt r equest is set, to indicate it is not operating at the desired frequency. then after yet ano ther 4096 xclk cycles followed regularly by 8192 xclk cycles (corre sponding to the 13-stage counter timing out), a che ck of the clock monitor status is performed. when the presence of an external cl ock is detected limp-home mode is exited generating a limp-home interrupt if enabled. caution: the clock monitor circuit can be misl ed by the extali clock into reporting a good signal before it has fully stabilised. under these conditions improper extali clock cycles can occur on sysclk. this may lead to a co de runaway. to ensur e that this situation does not occur, the external reset period s hould be longer than the oscillator stabilisation time - this is an application d ependent parameter. with the vddpll supply voltage at vss level, t he pll module and hence limp-home mode are di sabled, the device wil l remain effectively in a static state whilst there is no activity on ex tali. the internal reset period and mcu operation will execut e only on extali clock. note: the external clock signal must stabili se within the initial 4096 reset counter cycles.
clock functions technical data mc68hc9 12d60a ? rev. 3.1 148 clock functions freescale semiconductor 11.6.3 stop exit and fast stop recovery stop mode is entered when a stop instruction is executed. recovery from stop depends prim arily on the state of the three status bits nolhm, cme & dly. the dly bit controls t he duration of the wait ing period between the actual exit for some key blocks (e.g . clock monitor, clock generators) and the effective exit from stop for all the rest of the mc u. dly=1 enables the 13-stage counter to generate a 4096 count dela y. dly=0 selects no delay. as the xclk is derived from t he slow mode divide r, the value in the slow register modifies the actual delay time. note: dly=0 is only recommended when t here is a good si gnal available at the extal pin (e.g. an external squar e wave source). stop mode is exited with an external reset, an external interrupt from irq or xirq, a key wake -up interrupt from port j or port h, or an mscan wake-up interrupt.
clock functions limp-home and fast stop recovery modes mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor clock functions 149 figure 11-5. stop exit and fast stop recovery 11.6.4 stop exit without limp home mode, clock monitor disabled (nolhm=1, cme=0, dly=x) if limp home mode is disabled (v ddpll =v ss or nolhm bit set) and the cme (or fcme) bit is cleared, the mcu goes into stop mode when a stop instruction is executed. if extali clock is pres ent then exit from stop will occur normally using this clock. under this condition, dly should a lways be set to allow the crystal to stabilise and minimise th e risk of code runaway. with dly=1 execution resumes after a delay of 4096 xclk cycles. note: the external clock signal should stabilise within the 4096 reset counter cycles. use of dly=0 is not recommen ded due to this requirement. clock monitor fail extali 13-stage counter 0 --> 4096 limp-home (clocked by xclk) bcsp restore bcsp sysclk pllclk (l.h.) restore pllclk or extali stop (dly = 1) stop (dly = 0)
clock functions technical data mc68hc9 12d60a ? rev. 3.1 150 clock functions freescale semiconductor 11.6.5 executing the stop in struction without limp home mode, clock monitor enabled (nolhm=1, cme=1, dly=x) if the nolhm bit and t he cme (or fcme) bits ar e set, a clock monitor failure is detected when a stop instruction is executed and the mcu resets via the clock monitor reset vector. 11.6.6 stop exit in limp home mode with delay (nolhm=0, cme=x, dly=1) if the nolhm bit is cleared, then t he cme (or fcme) bit is masked when a stop instruction is executed to pr event a clock monitor failure. when coming out of stop mode, the mcu goes into limp-home mode where cme and fcme signals are asserted. when using a crystal oscillator, a normal stop exit sequence requires the dly bit to be set to allow for the crystal stabilization period. with the 13-stage counter clocked by the vco (at f vcomin ), following a delay of 4096 xclk cycles at the limp-home fr equency, if the clock monitor indicates the pres ence of an exte rnal clock, the limp-home mode is de-asserted and the mcu exits stop normally using extali clock. where the crystal start-up time is longer than the initial count of 4096 xclk cycles, or in the absence of an external clock, the mcu recovers from stop following the 4096 count in limp-ho me mode with both the lhome flag set and the lh if limp-home interrupt request set to indicate it is not operating at the desired frequency. ea ch time the 13-stage counter reaches a count of 4096 xclk cycles, a check of the clock monitor status is performed. when the presence of an external clo ck is detected, limp-home mode is exited and the lhome flag is cleared. this sets the limp-home interrupt flag and if enabled by th e lhie bit, the limp- home mode interrupt is requested. caution: the clock monitor circuit can be misled by extali clock into reporting a good signal before it has fully st abilised. under these conditions,
clock functions limp-home and fast stop recovery modes mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor clock functions 151 improper extali clock cycles can occur on sysclk. this may lead to a code runaway. 11.6.7 stop exit in limp home mode without delay ( fast stop recovery) (nolhm=0, cme=x, dly=0) fast stop recovery refers to any exit from stop using dly=0. if the nolhm bit is cleared, then t he cme (or fcme) bit is masked when a stop instruction is executed to pr event a clock monitor failure. when coming out of stop mode, the mcu goes into limp-home mode where cme and fcme signals are asserted. when using a crystal oscillator, it is possible to exit stop with the dly bit cleared. in this case, stop is de-asserted without delay and the mcu will execute software in limp-home mode, giving th e crystal oscillator time to stablise. caution: this mode is not recomm ended since the risk of the clock monitor detecting incorrect clocks is high.
clock functions technical data mc68hc9 12d60a ? rev. 3.1 152 clock functions freescale semiconductor each time the 13-stage counter reaches a count of 4096 xclk cycles (every 8192 cycles), a che ck of the clock monitor st atus is performed. if the clock monitor indicates the pres ence of an external clock limp-home mode is de-asserted, the lhome fl ag is cleared and the limp-home interrupt flag is set. upon leav ing limp-home mode, bcsp and mcs are restored to their values before the loss of clock, and all clocks return to their previous frequencies. if auto and bcsp were set before the clock loss, the sysclk ramps-up and the pll locks at t he previously selected frequency. to prevent pll operation when t he external clock frequency comes back, the software should clear t he bcsp bit while r unning in limp-home mode. when using an external clo ck, i.e. a square wave source, it is possible to exit stop with the dly bit cleare d. in this case the lhome flag is never set and stop is de -asserted without delay. 11.6.8 pseudo-stop pseudo-stop is a low pow er mode similar to stop where the external oscillator is allowed to run (at redu ced amplitude) whilst the rest of the part is in stop. this increases t he current consumption over stop mode by the amount of cu rrent in the oscillator, but reduces wear and mechanical stress on the crystal. if the pstp bit in the pllcr register is set, the mc u goes into pseudo- stop mode when a stop in struction is executed. pseudo-stop mode is exited the same as stop with an external reset, an external interrupt fr om irq or xirq, a key wake-up interrupt from port j or port h, or an mscan wake-up interrupt. the effect of the dly bit is the same as noted above in stop exit and fast stop recovery .
clock functions limp-home and fast stop recovery modes mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor clock functions 153 11.6.9 pseudo-stop exit in li mp home mode with delay (nolhm=0, cme=x, dly=1) when coming out of pseudo-stop mode with the no lhm bit cleared and the dly bit set, the mcu goes in to limp-home mode (regardless of the state of the cm e or fcme bits). the vco supplies the li mp-home clock frequen cy to the 13-stage counter (xclk). the bcsp output is forced high and mcs is forced low. after the 13-stage count er reaches a count of 4096 xclk cycles, a check of the clock monitor is perfor med and as the crystal oscillator was kept running due to the pseudo- stop mode, the mcu exits stop normally, using the extali clock. in the case where a crystal failure occurred during pseudo-st op, then the mcu exits stop using the limp home clock (f vcomin ) with both the lhome fl ag set and the lhif limp- home interrupt request set to indicate it is not operating at the desired frequency. each time the 13-stage counter reac hes a count of 4096 xclk cycles, a check of the clock monitor is perform ed. if the clock monitor indicates the presence of an ex ternal clock, limp-home mode is de-asserted, the lhome flag is cleared and the lhif limp-home interrupt request is set to indicate a return to normal operation using extali clock. 11.6.10 pseudo-stop exit in limp home mode without delay ( fast stop recovery) (nolhm=0, cme=x, dly=0) if pseudo-stop is exited with the nolh m bit set to 0 an d the dly bit is cleared then the exit fr om pseudo-stop is acco mplished without delay as in fast stop recovery. caution: where pseudo-stop recovers usi ng the limp home clock the vco - which has been held in stop - must be restarted in order to supply the limp home frequency. this restart, which occurs at a high frequency and ramps toward the limp home frequency, is almost immediately supplied to the cpu before it ma y have reached the steady state frequency. it is possible that the initial clock fr equency may be high enough to cause the cpu to function incorrectly with a resultant risk of code runaway.
clock functions technical data mc68hc9 12d60a ? rev. 3.1 154 clock functions freescale semiconductor 11.6.11 pseudo-stop exit without limp home m ode, clock monitor enabled (nolhm=1, cme=1, dly=x) if the nolhm bit is set and the cm e (or fcme) bits are set, a clock monitor failure is detected when a st op instruction is executed and the mcu resets via the clock monitor reset vector. 11.6.12 pseudo-stop exit without limp home m ode, clock monitor disabled (nolhm=1, cme=0, dly=1) if nolhm is set to 1 and the cme a nd fcme bits are cleared, the limp home clock is not used. in this mode, crystal activity is the only method by which the device may recover from pseudo-stop. the device will start execution with the extali clock following 4096 xclk cycles. (nolhm=1, cme=0, dly=0) if nolhm is set to 1 and the cme a nd fcme bits are cleared, the limp home clock is not used. in this mode, crystal activity is the only method by which the device may recover from pseudo-stop. the device will start execution with the extal i clock following 16 xclk cycles. caution: due to switching of the clock this configuration is not recommended. 11.6.13 11.6.14 summary of stop and pseudo-stop mode ex it conditions table 11-1 and table 11-2 summarise the exit conditions from stop and pseudo-stop modes using interr upt, key-interrupt and xirq. a short reset pulse shoul d not be used to exit stop or pseudo-stop mode because limp home mode is aut omatically entered after reset (when v ddpll =v dd ). the reset wakeup pulse mu st be longer than the oscillator startup time (as in power on reset) in order to remove the risk of code runaway.
clock functions limp-home and fast stop recovery modes mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor clock functions 155 .. table 11-1. summary of stop mode exit conditions mode conditions summary stop exit without limp home mode, clock monitor disabled nolhm=1 cme=0 dly=x oscillator must be stable wit hin 4096 xclk cycles. xclk can be modified by slow divider register. use of dly=0 only recommended with external clock. executing the stop instruction without limp home mode, clock monitor enabled nolhm=1 cme=1 dly=x when a stop instruction is executed the mcu resets via the clock monitor reset vector. stop exit in limp home mode with delay nolhm=0 cme=x dly=1 oscillator must be stable within 4096 f vcomin cycles or there is a possibility of code runaway as the clock monitor circuit can be misled by extali clock into reporting a good signal before it has fully stabilised stop exit in limp home mode without delay (fast stop recovery) nolhm=0 cme=x dly=0 this mode is only recommended for use with an external clock source. table 11-2. summary of p seudo stop mode exit conditions mode conditions summary pseudo-stop exit in limp home mode with delay nolhm=0 cme=x dly=1 cpu exits stop in limp home mo de and oscillator running. if the oscillator fails during pseudo-stop and then recovers there is a possibility of code runaway as the clock monitor circuit can be misled by extali clock into reporting a good signal before it has fully stabilised pseudo-stop exit in limp home mode without delay (fast stop recovery) nolhm=0 cme=x dly=0 this mode is not recommended as it is possible that the initial vco clock frequency may be high enough to cause code runaway. pseudo-stop exit without limp home mode, clock monitor enabled nolhm=1 cme=1 dly=x when a stop instruction is executed the mcu resets via the clock monitor reset vector. pseudo-stop exit without limp home mode, clock monitor disabled, with delay nolhm=1 cme=0 dly=1 oscillator starts operation following 4096 xclk cycles (actual controlled by slow mode divider). pseudo-stop exit without limp home mode, clock monitor disabled, without delay nolhm=1 cme=0 dly=0 this mode is only recommended for use with an external clock source.
clock functions technical data mc68hc9 12d60a ? rev. 3.1 156 clock functions freescale semiconductor 11.6.15 pll regi ster descriptions read anytime, write anytime, except when bcsp = 1 (pll selected as bus clock). if the pll is on, the count in the loop di vider (synr) register effectively multiplies up the bus frequency fr om the pll refe rence frequency by synr + 1. internally, sysclk runs at twice the bus frequency. caution should be used not to exceed the maximum ra ted operating frequency for the cpu. read anytime, write anyti me, except when bcsp = 1. the reference divider bits provides a finer granularity for the pll multiplier steps. the reference fr equency is divided by refdv + 1. always reads zero, exc ept in test modes. bit 7654321bit 0 0 0 syn5 syn4 syn3 syn2 syn1 syn0 reset: 00000000 synr ? synthesizer register $0038 bit 7654321bit 0 00000refdv2refdv1refdv0 reset: 0 0 0 0 0 0 0 0 refdv ? reference divider register $0039 bit 7654321bit 0 tstout7 tstout6 tstout5 tstout4 tstout3 tstout2 tstout1 tstout0 reset: 0 0 0 0 0 0 0 0 cgtflg ? clock generator test register $003a
clock functions limp-home and fast stop recovery modes mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor clock functions 157 read anytime, refer to eac h bit for write conditions. lockif ? pll lock interrupt flag 0 = no change in lock bit. 1 = lock condition has changed, either from a locked state to an unlocked state or vice versa. to clear the flag, write one to this bit in pllflg. cl eared in limp-home mode. lock ? locked phas e lock loop circuit regardless of the bandwidth contro l mode (automatic or manual): 0 = pll vco is not within the des ired tolerance of the target frequency. 1 = after the phase lock l oop circuit is turned on, indi cates the pll vco is within the desired tole rance of the target frequency. write has no effect on lock bit. this bit is cleare d in limp-home mode as the lock detector c annot operate without t he reference frequency. lhif ? limp-home interrupt flag 0 = no change in lhome bit. 1 = lhome condition has changed, either entered or exited limp- home mode. to clear the flag, write one to this bit in pllflg. lhome ? limp-home mode status 0 = mcu is operating normally, wi th extali clock available for generating clocks or as pll reference. 1 = loss of reference clock. cgm delivers pll vco limp-home frequency to the mcu. for limp-home mode, see limp-home and fast stop recovery modes . bit 7654321bit 0 lockiflock0000lhiflhome reset: 00000000 pllflg ? pll flags $003b
clock functions technical data mc68hc9 12d60a ? rev. 3.1 158 clock functions freescale semiconductor read and write anytime . exceptions are list ed below for each bit. lockie ? pll lock interrupt enable 0 = pll lock interrupt is disabled 1 = pll lock interrupt is enabled forced to 0 when vddpll=0. pllon ? phase lock loop on 0 = turns the pll off. 1 = turns on the phase lock loop circui t. if auto is se t, the pll will lock automatically. cannot be cleared when bcsp = 1 (pll selected as bus clock). forced to 0 when vddpll is at vss level. in limp-home mode, the output of pllon is forced to 1, but the pllon bit reads the latched value. auto ? automatic bandwidth control 0 = automatic mode control is disabled and the pll is under software control, using acq bit. 1 = automatic mode con trol is enabled. acq bit is read only. automatic bandwidth control sele cts either the high bandwidth (acquisition) mode or the low bandwidth (tracking) mode depending on how close to the desired freque ncy the vco is running. see electrical specifications . bit 7654321bit 0 lockie pllon auto acq 0 pstp lhie nolhm reset: 0 ? (1) 10000 ? (2) pllcr ? pll control register $003c 1. set when vddpll power supply is high. forced to 0 when vddpll is low. 2. cleared when vddpll power supply is high. forced to 1 when vddpll is low.
clock functions limp-home and fast stop recovery modes mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor clock functions 159 acq ? not in acquisition if auto = 1 (acq is read only) 0 = pll vco is not within the des ired tolerance of the target frequency. the loop filter is in high bandwidth, acquisition mode. 1 = after the phase lock l oop circuit is turned on, indi cates the pll vco is within the desired tole rance of the target frequency. the loop filter is in lo w bandwidth, tracking mode. if auto = 0 0 = high bandwidth pll loop selected 1 = low bandwidth pll loop selected pstp ? pseudo- stop enable 0 = pseudo-stop oscilla tor mode is disabled 1 = pseudo-stop osci llator mode is enabled in pseudo-stop mode, the oscillator is still r unning while the mcu is maintained in stop m ode. this allows for a faster stop recovery and reduces the mechanical stress and aging of the resonator in case frequent stop conditions at the expense of a sl ightly increased power consumption. lhie ? limp-home interrupt enable 0 = limp-home inte rrupt is disabled 1 = limp-home inte rrupt is enabled forced to 0 when vddpll is at vss level. nolhm ?no limp-home mode 0 = loss of reference clock forc es the mcu in limp-home mode. 1 = loss of reference clock caus es standard clock monitor reset. read anytime; normal modes: wr ite once; special modes: write anytime. forced to 1 when vddpll is at vss level.
clock functions technical data mc68hc9 12d60a ? rev. 3.1 160 clock functions freescale semiconductor read and write anytime . exceptions are list ed below for each bit. bcsp and bcss bits dete rmine the clock used by the main system including the cpu and buses. bcsp ? bus clock select pll 0 = sysclk is derived from the crystal clock or from slwclk. 1 = sysclk source is the pll. cannot be set when pllon = 0. in limp-home mode, the output of bcsp is forced to 1, but the b csp bit reads the latched value. bcss ? bus clock select slow 0 = sysclk is derived from the crystal clock extali. 1 = sysclk source is the slow clock slwclk. this bit has no effect when bcsp is set. mcs ? module clock select 0 = m clock is the same as pclk. 1 = m clock is derived from slow clock slwclk. this bit determines t he clock used by the ect module and the baud rate generators of the scis. in limp-home mode , the output of mcs is forced to 0, but the mcs bit reads the latched value. bit 7654321bit 0 0 bcsp bcss 0 0 mcs 0 0 reset: 00000000 clksel ? clock generator clock select register $003d
clock functions limp-home and fast stop recovery modes mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor clock functions 161 read and write anytime. a write to this register changes the slwclk frequency with minimum delay (less than one slwclk cycl e), thus allowi ng immediate tune- up of the performance versus po wer consumption for the modules using this clock. the frequency divide ratio is 2 times (slow), hence the divide range is 2 to 126 ( not on first pass products). when slow = 0, the divider is bypass ed. the generation of e, p and m clocks further divides sl wclk by 2. hence, t he final ratio of bus to extali frequency is prog rammable to 2, 4, 8, 12, 16, 20, ..., 252, by steps of 4. slwclk is a 50% duty cycle signal. bit 7654321bit 0 0 0 sldv5 sldv4 sldv3 sldv2 sldv1 sldv0 reset: 00000000 slow ? slow mode divider register $003e
clock functions technical data mc68hc9 12d60a ? rev. 3.1 162 clock functions freescale semiconductor 11.7 system clock frequency formulas see figure 11-6 : slwclk = extali / ( 2 x slow ) slow = 1,2,..63 slwclk = extali slow = 0 pllclk = 2 x extali x (synr + 1) / (refdv + 1) eclk = sysclk / 2 xclk = slwclk / 2 pclk = sysclk / 2 bclk (1) = extali / 2 boolean equations: sysclk = (bcsp & pllclk) | (bcsp & bcss & extali) | (bcsp & bcss & slwclk) mclk = (pclk & mcs ) | (xclk & mcs) mscan system = ( extali & clksrc) | (sysclk & clksrc) bdm system = (bclk & clksw) | (eclk & clksw) note: during limp-home m ode pclk, eclk, bclk, mclk and xclk are supplied by vco (pllclk). 11.8 clock divider chains figure 11-6 , figure 11-7 , figure 11-8 , and figure 11-9 summarize the clock divider chains for t he various peripherals on the mc68hc912d60a. 1. if sysclk is slower than extali (bcss= 1, bcsp=0, slow>0), bclk becomes eclk.
clock functions clock divider chains mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor clock functions 163 figure 11-6. clock generation chain bus clock select bits bcsp and bcss in the clock select register (clksel) determine which clock dr ives sysclk for the main system including the cpu and buses . bcss has no effect if bcsp is set. during reduced consumption oscillator phase lock loop extal xtal 0:0 sysclk to buses, spi, pwm, atd0, atd1 to rti, cop bcsp bcss slow mode clock divider extali extali extali slwclk pllclk 0:1 bcsp bcss 1:x bcsp bcss mcs = 0 mcs = 1 2 2 to mscan clksrc = 1 tclks t clock generator e and p clock generator pclk eclk xclk to sci0, sci1, ect to cpu sync mclk to bdm 2 sync to cal to clock monitor clksrc = 0 clksw = 0 clksw = 1 bdmclk
clock functions technical data mc68hc9 12d60a ? rev. 3.1 164 clock functions freescale semiconductor the transition, the clock se lect output will be held low and all cpu activity will cease until the trans ition is complete. the module clock select bit mcs deter mines the clock used by the ect module and the baud rate generators of the scis . in limp-home mode, the output of mcs is forced to 0, but the mcs bit reads the latched value. it allows normal operati on of the serial and time r subsystems at a fixed reference frequen cy while allowing the cpu to operate at a higher, variable frequency. figure 11-7. clock chain fo r sci0, sci1, rti, cop xclk sc0bd modulus divider: 1, 2, 3, 4, 5, 6,...,8190, 8191 sci0 receive baud rate (16x) sci0 transmit baud rate (1x) bits: rtr2, rtr1, rtr0 to rti bits: cr2, cr1, cr0 to cop 16 sci1 receive baud rate (16x) sci1 transmit baud rate (1x) 16 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 2 2 2 2 2 2 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 4 4 4 2 4 2 4 register: copctl register: rtictl sc1bd modulus divider: 1, 2, 3, 4, 5, 6,...,8190, 8191 register: rtictl bit:rtbyp 2048 mclk
clock functions clock divider chains mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor clock functions 165 figure 11-8. clock chain for ect bits: pr2, pr1, pr0 mclk pamod paclk pulse acc low byte paclk/256 pulse acc high byte paclk/65536 (paov) gate logic bits: paen, clk1, clk0 ten register: pactl register: tmsk2 paen 0:0:0 0:0:1 2 0:1:0 2 0:1:1 2 1:0:0 2 1:0:1 2 1:1:0 2 1:1:1 2 bits: mcpr1, mcpr0 mcen register: mcctl 0:0 0:1 4 1:0 2 1:1 2 0:x:x 1:0:0 1:0:1 1:1:0 1:1:1 to timer main counter (tcnt) modulus down counter port t7 prescaled mclk
clock functions technical data mc68hc9 12d60a ? rev. 3.1 166 clock functions freescale semiconductor figure 11-9. clock chain for m scan, spi, atd0 , atd1 and bdm 11.9 computer oper ating properly (cop) the cop or watchdog timer is an added check that a program is running and sequencing properly. when the cop is being used, software is responsible for keeping a free running watchdog timer fr om timing out. if the watchdog timer times out it is an indication that t he software is no longer being executed in the intended sequence; thus a system reset is initiated. three control bits allow selection of seve n cop time-out periods. when cop is e nabled, sometime during the selected period the program must write $55 an d $aa (in this order) to the coprst register. if the program fails to do this the part will rese t. if any val ue other than $55 or $aa is written, the part is reset. pclk bits : spr2, spr1, spr0 spi bit rate 5-bit modulus counter (pr0-pr4) to atd0 and atd1 bkgd bdm bit clock: receive: detect falling edge, count 12 eclks, sample input transmit 1: detect falling edge, count 6 eclks while output is high impedance, drive out 1 e cycle pulse high, high imped- ance output again transmit 0: detect falling edge, drive out low, count 9 eclks, drive out 1 e cycle pulse high, high impedance output pin synchronizer logic bkgd in bkgd out bkgd direction 2 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 2 2 2 2 2 2 2 2 register: sp0br mscan clock clksrc extali sysclk clksw eclk bclk
clock functions real-time interrupt mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor clock functions 167 in addition, window ed cop operation can be se lected. in this mode, writes to the coprst regi ster must occur in the la st 25% of the selected period. a premature write will also reset the part. 11.10 real-time interrupt there is a real time ( periodic) interrupt avai lable to the user. this interrupt will occur at on e of seven selected rate s. an interrupt flag and an interrupt enable bit are associated wi th this function. there are three bits for the rate select. 11.11 clock monitor the clock monitor circuit is based on an internal resistor-capacitor (rc) time delay. if no extali clock edges are detected within this rc time delay, the clock monitor can optio nally generate a syst em reset. the clock monitor function is enabled/disa bled by the cme control bit in the copctl register. this time -out is based on an rc delay so that the clock monitor can operate without any extali clock. clock monitor time-outs are shown in table 11-3 . the corresponding extali clock period with an ideal 50% duty cycle is twice this time-out value. table 11-3. clock monitor time-outs supply range 5 v +/? 10% 2?20 s
clock functions technical data mc68hc9 12d60a ? rev. 3.1 168 clock functions freescale semiconductor 11.12 clock function registers all register addresses shown reflect the reset state. registers may be mapped to any 2k byte space. rtie ? real time interrupt enable read and write anytime. 0 = interrupt requests from rti are disabled. 1 = interrupt will be requeste d whenever rtif is set. rswai ? rti and cop st op while in wait write once in normal modes, an ytime in special modes. read anytime. 0 = allows the rti and cop to continue running in wait. 1 = disables both the rti and co p whenever the part goes into wait. rsbck ? rti and co p stop while in ba ckground debug mode write once in normal modes, an ytime in special modes. read anytime. 0 = allows the rti and cop to continue running while in background mode. 1 = disables both t he rti and cop when the part is in background mode. this is useful for emulation. rtbyp ? real time interr upt divider chain bypass write not allowed in normal modes, anytime in special modes. read anytime. 0 = divider chain functions normally. 1 = divider chain is by passed, allows faster testing (the divider chain is normally xclk divided by 2 13 , when bypassed becomes xclk divided by 4). bit 7654321bit 0 rtie rswai rsbck reserved rtbyp rtr2 rtr1 rtr0 reset: 00000000 rtictl ? real-time interrupt control register $0014
clock functions clock function registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor clock functions 169 rtr2, rtr1, rtr0 ? real-time interrupt rate select read and write anytime. rate select for real-time interrupt . the clock used for this module is the xclk. rtif ? real time interrupt flag this bit is cleared aut omatically by a write to th is register with this bit set. 0 = time-out has not yet occurred. 1 = set when the time -out period is met. table 11-4. real time interrupt rates rtr2 rtr1 rtr0 divide x by: time-out period x = 125 khz time-out period x = 500 khz time-out period x = 2.0 mhz time-out period x = 8.0 mhz 0 0 0 off off off off off 001 2 13 65.536 ms 16.384 ms 4.096 ms 1.024 ms 010 2 14 131.72 ms 32.768 ms 8.196 ms 2.048 ms 011 2 15 263.44 ms 65.536 ms 16.384 ms 4.096 ms 100 2 16 526.88 ms 131.72 ms 32.768 ms 8.196 ms 101 2 17 1.05 s 263.44 ms 65.536 ms 16.384 ms 110 2 18 2.11 s 526.88 ms 131.72 ms 32.768 ms 111 2 19 4.22 s 1.05 s 263.44 ms 65.536 ms bit 7654321bit 0 rtif0000000 reset: 00000000 rtiflg ? real time interrupt flag register $0015
clock functions technical data mc68hc9 12d60a ? rev. 3.1 170 clock functions freescale semiconductor cme ? clock monitor enable read and write anytime. if fcme is set, this bit has no meaning nor effect. 0 = clock monitor is disabled. sl ow clocks and stop instruction may be used. 1 = slow or stopped clocks (incl uding the stop instruction) will cause a clock reset sequenc e or limp-home mode. see limp- home and fast stop recovery modes . on reset cme is 1 if vddpll is high cme is 0 if vddpll is low. note: the vddpll-dependent reset operation is not im plemented on first pass products. in this case the stat e of cme on reset is 0. fcme ? force clock monitor enable write once in normal modes, an ytime in special modes. read anytime. in normal modes, when this bit is set, the clock monitor function cannot be disabled until a reset occurs. 0 = clock monitor follows the state of the cme bit. 1 = slow or stopped clocks will c ause a clock reset sequence or limp-home mode. see limp-home and fast stop recovery modes . bit 7654321bit 0 cme fcme fcmcop wcop disr cr2 cr1 cr0 reset: 0/1 0 0 0 0 1 1 1 normal reset: 0/1 0 0 0 1 1 1 1 special copctl ? cop control register $0016
clock functions clock function registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor clock functions 171 fcmcop ? force clock monitor reset or cop watchdog reset writes are not allowed in normal modes, anytime in special modes. read anytime. if disr is set, th is bit has no effect. 0 = normal operation. 1 = a clock monitor failure reset or a cop failure reset is forced depending on the state of cme and if cop is enabled. wcop ? window cop mode write once in normal modes, an ytime in special modes. read anytime. 0 = normal cop operation 1 = window cop operation when set, a write to the coprst regi ster must occur in the last 25% of the selected period. a premature write will also reset the part. as long as all writes occur during this window, $55 can be written as often as desired. once $aa is written the time-out logic restarts and the user must wait until the next window before writ ing to coprst. please note, there is a fixed time uncertainty about the exact cop counter state when reset, as the initial prescale clock divider in the rti section is not cl eared when the cop coun ter is cleared. this means the effective window is reduced by this uncertainty. table 11- 5 below shows the exact duration of this window for the seven available cop rates. cme cop enabled forced reset 0 0 none 0 1 cop failure 1 0 clock monitor failure 11 both (1) 1. highest priority inte rrupt vector is serviced.
clock functions technical data mc68hc9 12d60a ? rev. 3.1 172 clock functions freescale semiconductor disr ? disable resets from cop watchdog and clock monitor writes are not allowed in normal modes, anytime in special modes. read anytime. 0 = normal operation. 1 = regardless of other control bi t states, cop and clock monitor will not generate a system reset. cr2, cr1, cr0 ? cop watchdog timer rate select bits these bits select the cop time- out rate. the clock used for this module is the xclk. write once in normal modes, an ytime in special modes. read anytime. table 11-5. cop watchdog rates cr2 cr1 cr0 divide x clock by 8.0 mhz x clock. time-out window cop enabled: window start (1) window end effective window (2) 0 0 0 off off off off off 001 2 13 1.024 ms -0/+0.256 ms 0.768 ms 0.768 ms 0% (3) 010 2 15 4.096 ms -0/+0.256 ms 3.072 ms 3.840 ms 18.8 % 011 2 17 16.384 ms -0/+0.256 ms 12.288 ms 16.128 ms 23.4 % 100 2 19 65.536 ms -0/+1.024 ms 49.152 ms 64.512 ms 23.4 % 101 2 21 262.144 ms -0/+1.024 ms 196.608 ms 261.120 ms 24.6 % 110 2 22 524.288 ms -0/+1.024 ms 393.216 ms 523.264 ms 24.8 % 111 2 23 1.048576 ms -0/+1.024 ms 786.432 ms 1.047552 s 24.9 % 1. time for writing $55 following previous co p restart of time-out logic due to writing $aa. 2. please refer to wcop bit description above. 3. window cop cannot be used at this rate.
clock functions technical data mc68hc9 12d60a ? rev. 3.1 173 clock functions freescale semiconductor always reads $00. writing $55 to this address is the first step of the cop watchdog sequence. writing $aa to this address is t he second step of the cop watchdog sequence. other instruct ions may be executed between these writes but both must be complete d in the correct order prior to time-out to avoid a watchdog reset. writing anything other than $55 or $aa causes a cop reset to occur. bit 7654321bit 0 bit 7654321bit 0 reset: 00000000 coprst ? arm/reset cop timer register $0017
clock functions technical data mc68hc9 12d60a ? rev. 3.1 174 clock functions freescale semiconductor
oscillator contents mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor oscillator 175 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 12.3 mc68hc912d60a oscillator specification. . . . . . . . . . . . . . . 176 12.4 mc68hc912d60c colpitts oscillator specification . . . . . . . . 179 12.5 mc68hc912d60p pierce oscillator s pecification . . . . . . . . . 194 12.2 introduction the oscillator implementati on on the original 0.65 (non-suffix) hc12 d- family is a ?colpitts oscillator with translated ground?. this design was carried over to the first 0.5 devices (a-suffix), up to the 1l02h mask set, and is described in section 12.3 mc68hc912d60a oscillator specification . in this section of the document, the term mc68hc912d60a refers only to the mc68hc912d60a device. on mask set 2l02h, the colpitts osci llator was updated , primarily to improve its performance. to maximi se the benefit of this change, different external component valu es are required. however, the oscillator will per form at least as well as the mc68hc912d60a version with the same components. this implementation and the changes are described in section 12.4 mc68hc912d60c colpitts oscillator specification . in order to make the hc12 d-family oscillator options more flexible, a pierce oscillator configuratio n has been implemented on the 3l02h mask set. this implementat ion, described in section 12.5 mc68hc912d60p pierce osci llator specification , utilises the automatic technical data ? mc68hc912d60a section 12. oscillator
oscillator technical data mc68hc9 12d60a ? rev. 3.1 176 oscillator freesca le semiconductor level control circuit to provide a lowe r power oscillator than traditional pierce oscillators based on simple inverter circuits. in the following sections, each parti cular oscillator implementation is described in detail. refer to the appr opriate sections for the mask set being used and optimum exte rnal component selection. 12.3 mc68hc912d60a o scillator specification this section applies to the 1l02h mask se t and all previous mc68hc912d60a versions. 12.3.1 mc68hc912d60a oscillator desi gn architecture the colpitts oscillator ar chitecture is shown in figure 12-1 . the component configuration for this oscillator is the same as all previous mc68hc912d60a configurations.
oscillator mc68hc912d60a oscilla tor specification mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor oscillator 177 figure 12-1. mc68hc912d60a colpitts oscillator architecture 12.3.2 mc68hc912d60a oscillator desi gn guidelines proper and robust operation of the o scillator circuit requires excellent board layout design practice. poor la yout of the appl ication board can contribute to emc susceptibility, noise generation, slow starting oscillators, and reaction to noise on the clock input buff er. in addition to published errata for the mc68hc912d 60a, the following guidelines must be followed or fail ure in operation may occur. alc + - ota + - cflt rflt en bias resonator c x-ex c x-vss buf rflt cflt 2 gm extal xtal resd
oscillator technical data mc68hc9 12d60a ? rev. 3.1 178 oscillator freesca le semiconductor minimize capacitance to vss on extal pin ? the colpitts oscillator architecture is sensitiv e to capacitance in parallel with the resonator (from extal to vss). follow these techniques: i. remove ground plane from all layers around resonator and extal route ii. observe a minimum spacing fr om the extal trace to all other traces of at least three times the design rule minimum (until the mi crocontroller?s pin pitch prohibits this guideline) iii. where possible, use xtal as a shield between extal and vss iv. keep extal capacitanc e to less than 1pf (2pf absolute maximum) shield all oscillator com ponents from all noisy traces (while observing above guideline). keep the vsspll pin and the vss reference to the oscillator as identical as possible . impedance between these signals must be minimum. observe best pract ice supply bypassing on all mcu power pins. the oscillator?s supply reference is vdd, not vddpll. account for xtal?vss and extal?xtal parasitics in component values. note: an increase in the extal ? xtal parasitic as a result of reducing extal ? vss parasitic is acceptable provided component value is reduced by the appr opriate value. minimize xtal and extal routing lengths to reduce emc issues. note: extal and xtal routing resistan ces are less important than capacitances. using minimum width tr aces is an acceptable trade-off to reduce capacitance.
oscillator mc68hc912d60c colpitts oscillator specification mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor oscillator 179 12.4 mc68hc912d60c colpit ts oscillator specification this section applies to t he 2l02h mask set, whic h refers to the newest set of cgm improvements (to the mc68hc912d60a) with the colpitts oscillator configuration enabled. the name for these devices is mc68hc912d60c. 12.4.1 mc68hc912d60c oscillator design architecture the colpitts oscillator ar chitecture is shown in figure 12-2 . the component configuration for this oscillator is the same as all previous mc68hc912d60a configurations.
oscillator technical data mc68hc9 12d60a ? rev. 3.1 180 oscillator freesca le semiconductor figure 12-2. mc68hc912d60c colp itts oscillator architecture there are the following pr imary differences betw een the previous (?a?) and new (?c?) colpitts oscillator configurations: hysteresis was added to the clock in put buffer to reduce sensitivity to noise internal parasitics were reduc ed from extal to vss to increase oscillator gain margin. alc + - ota + - cflt rflt en bias resonator c x-ex c x-vss buf rflt cflt 2 gm extal xtal resd
oscillator mc68hc912d60c colpitts oscillator specification mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor oscillator 181 the bias current to the amplifier was optimized for less variation over process. the input esd resistor from extal to the gate of the oscillator amplifier was changed to provi de a parallel path, reducing parasitic phase shift in the oscillator. 12.4.1.1 clock bu ffer hysteresis the input clock buffer uses an oper ational transconductance amplifier (labeled ?ota? in the figure above) followed by a di gital buffer to amplify the input signal on the extal pin into a full-swing clo ck for use by the clock generation section of the microcontroller. ther e is an internal r-c filter (composed of co mponents rflt2 and cflt2 in the figure above), which creates the dc value to whic h the extal signal is compared. in this manner, the clock input buffer can track changes in the extal bias voltage due to process vari ation as well as exter nal factors such as leakage. because the purpose of the clock input buffer is to amplify relatively low- swing signals into a full-r ail output, the gain of t he ota is very high. in the configuration shown, this means t hat very small levels of noise can be coupled onto the i nput of the clock buffe r resulting in noise amplification. to remedy this issue, hysteresis was added to the ota so that the circuit could still provide the tolerance to leakage and the high gain required without the noise sensit ivity. approximately 150m v of hysteresis was added with a maximum hysteresis over process variation of 350mv. as such, the clock input buffe r will not respond to input signals until they exceed the hysteresis level. at th is point, the inpu t signal due to oscillation will dominate the total input waveform and narrow clock pulses due to noise will be eliminated. this circuit will limit the overall performance of the oscillator block only in cases where the amplitude of os cillation is less than the level of hysteresis. the minimum amplitude of o scillation is expected to be in excess of 750mv and the maximum hyst eresis is expected to be less than 350mv, providing a factor of safety in excess of two.
oscillator technical data mc68hc9 12d60a ? rev. 3.1 182 oscillator freesca le semiconductor 12.4.1.2 internal parasitic reduction any oscillator circuit?s gain marg in is reduced when a low ac-impedance (low resistance or high capacitance) is placed in pa rallel with the resonator. in the colpitts oscillato r configuration, this impedance is dominated by the parasit ic capacitance from t he extal pin to vss. since this capacitance is large comp ared to the shunt capacitance of the resonator, the gain margin in a colpitts configuration is less than in other configurations. to remedy this issue, the internal circuits were optimized for lower capacitance. this should increase the gain margin and allow more robust operation over pr ocess, temperature a nd voltage vari ation. to maximize the benefit of th is change, different exte rnal component values are required. however, the oscillator will function at least as well as the mc68hc912d60a version with the same components. 12.4.1.3 bias curren t process optimization for proper oscillation, the gain margin of the oscillator must exceed one or the circuit will not o scillate. due to the sens itive gain margin of the colpitts configuration, process va riance in the bias current (which controls the gain of the amplifier) can cause the gain margin to be much lower than typical. this can be as a resu lt of either too much or too little current. to reduce the process sensitivity of t he gain, the material of the device that sets the bias current was changed to a material with tighter process and temperature control. as a result, the tran sconductance and ibias variances are more limited t han in the prev ious design.
oscillator mc68hc912d60c colpitts oscillator specification mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor oscillator 183 12.4.1.4 input esd resist or path modification to satisfy the condition of oscillation, the oscillator circ uit must not only provide the correct amount of gain but also the correct amount of phase shift. in the colpitts configuration, the phase shift due to parasitics in the input path to the gate of the transc onductance amplifier must be as low as possible. in the origi nal configuration, the par asitic capacitance of the clock input buffer (ota), automatic loop control circuit (alc), and input resistors (rflt and rflt2) reacted with the input resistance to cause a large phase shift. to reduce the phase shift, the input esd resi stor (marked resd in the figure above) was changed from a single path to the input circuitry (the alc and the ota) and oscillator tr ansconductance amplifier (marked gm in the figure above) to a parallel path. in this configuration, the only capacitance causing a phase shift on t he input to the transconductance device is due to the transc onductance device itself.
oscillator technical data mc68hc9 12d60a ? rev. 3.1 184 oscillator freesca le semiconductor 12.4.2 mc68hc912d60c oscillator cir cuit specifications 12.4.2.1 negative resistance margin negative resistance marg in (nrm) is a figure of merit commonly used to qualify an oscillator ci rcuit with a given resona tor. nrm is an indicator of how much additional resistance in series with the resonator is tolerable while still maintaining oscilla tion. this figure is usually expected to be a multiple of the nominal "maximum" rate d esr of the resonator to allow for variation and degr adation of the resonator. currently, many systems are optimiz ed for nrm by ad justing the load capacitors until nrm is maximized. this method may not achieve the best overall nrm because the optimiz ation method is empirical and not analytical. that is, the method only achieves the best nrm for the particular sample set of microcontrollers, res onators, and board values tested. the figure below shows the anticipated nr m for a nominal 4mhz resonator given the expected proce ss variance of the microcontroller (d60a), board, and crystal (excluding es r). in this case, the value of load capacitors providing the optim um nrm for a best- case situation yield an unacceptable nr m for a worst-case sit uation (the slope of the nrm vs. capacitance curve is very steep, indicating severe sensitivity to small variations). if the nrm opt imization happened to be performed on a best-case sample set, there coul d be unexpected sensitivity at worst- case. negative resistance margin vs. capacitance 10 100 1000 68 56 47 39 33 27 22 18 15 13 10 8 capacitance negative resistance margin wcs ty p ty p bcs
oscillator mc68hc912d60c colpitts oscillator specification mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor oscillator 185 nrm measurement techni ques can also generat e misleading results when applied to automati c level control (alc) st yle oscillator circuits such as the d60x/dx128x. many nr m methods slowly increase series resistance until oscillation stops. al c-style oscillators reduce the gain of the oscillator circui t after start-up to reduce curr ent, so if the oscillator tends to have more gain than optimum it will be more tolerant of additional resistance after start-up than it will during the start-up process. this means that nrm figures may be optimistic unless the method verifies the nrm value by attempting to start the oscillator with the additional resistance in-place. wo rse, this phenomenon exaggerates the difference between best- and worst-case nrm curves. 12.4.2.2 gain margin the gain margin of the o scillator indicates the am ount the gain of the oscillator can vary while maintaini ng oscillation. s pecifically, gain margin is: gain margin = min(gain/minimum required gain, maximum allowed gain/gain) just like nrm, gain margin may be dominated by either too much or too little oscillator gain a nd an increase in gain may not increase gain margin. gain margin is theoretically related to nrm since the maximum allowed gain is (approximately) in versely proportiona l to esr, and the minimum required gain is (approximately) proporti onal to esr, leaving gain margin (approx imately) inversely proportional to esr. the preferred method for specifying th e oscillator, give n a set of load capacitor values, is to determi ne the maximum allowed esr while maintaining a worst-case gain marg in of 2. since gain margin is proportional to esr, this means the empirica lly measured nrm at the worst-case point would be approx imately twice the maximum allowed esr. however, since typical nr m is likely to be higher and most measurement techniques do not account for alc effects, actual nrm measurements are likely to be much higher.
oscillator technical data mc68hc9 12d60a ? rev. 3.1 186 oscillator freesca le semiconductor 12.4.2.3 optimizi ng component values the maximum esr possible (given a worst- case gain margin of 2) is not the optimum operat ing point. in some cases, the frequency accuracy of the oscillator is important and in other cases satisfying the traditional nrm measurement tec hnique is important. if frequency accuracy is important , the total load capacitance (the combination of the load capacitors and their a ssociated parasitics) should be equal (or close to equal) to the rat ed load capacitance of the resonator. provided the resultant load capacitors yield a maximum allowed esr greater than the maxi mum esr of the crystal (while maintaining the worst case gain marg in of 2), this is an acceptable operating point. if the maximum al lowed esr is not high enough, the closest possible components with high enough esr should be chosen. similarly, if meeting a tr aditional nrm optimization criteria is important, then the components determ ined by this method are acceptable if the same components yiel d a maximum allowed esr greater than the maximum esr of the cryst al while maintaining the worst case gain margin of 2. there is no guaran tee that component s chosen through traditional nrm optimizat ion techniques wi ll yield acceptable results across all expected variations. 12.4.2.4 key parameters the following items are of critical importance to the operation of the oscillator: extal ? xtal capacitor value ? the value of the component plus external (board) parasitic in excess of 0. 1pf between extal and xtal. xtal ? vss capacitor value ? the value of t he component plus external (board) parasitic in excess of 1.0pf bet ween xtal and vss. maximum shunt capacitance ? the maximum value of the resonator?s shunt capac itance (c0) plus t he external (board) parasitics in excess of 1pf from exta l to vss.
oscillator mc68hc912d60c colpitts oscillator specification mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor oscillator 187 vddpll setting ? the voltage applied to the vddpll pin (logic 1 means vddpll is tied to the same potential as vdd). resonator frequency ? the frequency of o scillation of the resonator. maximum esr ? the maximum effectiv e series resistance (esr) of the resonator. this figur e must include any increases due to ageing, power dissipation, temperature, process variation or particle contamination. 12.4.3 important information for calculating component values before attempting to apply the informati on in section 12.4.2.4 key parameters , the following data from the resonator vendor is required: resonator frequency (f) maximum esr (r , esr, or r1) maximum shunt capacitance (c0) load capacitance (cl) ? this is not th e external component values but rather t he capacitance applied in parallel with the resonator during th e tuning procedure. 12.4.3.1 how to use this information the following tables provide maxi mum esr vs. com ponent value for various frequencies. this table should be used in the following manner: 1. choose the set of component va lues corresponding to the correct maximum shunt c apacitance (equa l to the sum of extal?vss parasitics in excess of 1pf, plus the c0 of the resonator) and vddpll setting. 2. determine the range of compone nts for which the maximum esr is greater than the absolute maximum esr of the resonator (including ageing, power dissipat ion, temperature, process
oscillator technical data mc68hc9 12d60a ? rev. 3.1 188 oscillator freesca le semiconductor variation or particle contamination). 3. within this range, choose the extal?xtal capacitance closest to (c extal?xtal = 2*cl ? 1pf). 4. if the ideal component is betw een two valid component values (the maximum esr is sufficient for both component values), then choose the component with the highest maximum esr or choose an available component betw een the two listed values. 5. choose the size of the xtal ?vss capacitance equal to the closest available size to (c xtal?vss = 0.82*c extal?xtal ). 6. if the frequency of the crystal falls between listed values, determine the appropriate com ponent for the li sted frequency values on either side and extrapolate. 7. the maximum allowed capacitor is the highest listed component, and the minimum allo wed capacitor is the lowest listed component. ?na? or ?not allowed? means t he listed component is not valid or allowed for the giv en frequency, shunt capacitance, and vddpll setting. 12.4.3.2 general specifications the following limitations apply to every system: ceramic resonators with in tegrated components should not be used, as they are designed for pierce-configured oscillators. series cut resonators should not be used. use parall el cut instead. the load capacitance should be 12pf or higher, preferably greater than 15pf.
oscillator mc68hc912d60c colpitts oscillator specification mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor oscillator 189 table 12-1. mc68hc912d60c extal ? xtal capacitor values vs. maximum esr, shunt capacitance, and vddpll setting maximum esr vs. extal?xtal capacitor value, 1mhz resonators shunt capacitance (pf) (vddpll=vdd) 3 1570 2080 2620 2700 1870 1140 630 170 5 1460 1890 2340 2010 1370 830 460 120 7 1350 1730 2100 1550 1050 630 350 90 10 1210 1520 1600 1100 740 440 240 60 c extal-xtal (pf) 100pf 82pf 68pf 56pf 47pf 39pf 33pf 27pf 22pf 18pf maximum esr vs. extal?xtal capacitor value, 2mhz resonators shunt capacitance (pf) (vddpll=vdd) 3 360 480 620 780 940 1100 1080 730 440 240 5 340 450 570 700 830 950 800 530 320 170 7 320 410 520 630 740 830 620 410 250 130 10 290 370 450 550 620 600 440 290 170 90 c extal-xtal (pf) 100pf 82pf 68pf 56pf 47pf 39pf 33pf 27pf 22pf 18pf maximum esr vs. extal?xtal capacitor value, 4mhz resonators shunt capacitance (pf) (vddpll=vdd) 3 210 255 290 335 370 340 175 80 5 190 225 254 290 310 255 130 60 7 170 200 227 250 270 200 100 45 10 145 170 190 205 205 140 70 25 shunt capacitance (pf) (vddpll=0) 3 250 300 350 400 440 325 165 75 5 225 265 305 340 345 245 120 55 7 200 235 265 295 270 190 90 40 10 175 200 220 240 195 135 65 20 c extal-xtal (pf) 47pf 39pf 33pf 27pf 22pf 18pf 13pf 10pf
oscillator technical data mc68hc9 12d60a ? rev. 3.1 190 oscillator freesca le semiconductor maximum esr vs. extal?xtal capacitor value, 8mhz resonators shunt capacitance (pf) (vddpll=vdd) 3 40 50 60 70 80 90 95 90 5 35 45 50 60 70 75 80 70 7 30 40 45 50 60 65 65 10 25 30 35 40 45 50 shunt capacitance (pf) (vddpll=0) 3 50 60 70 85 95 105 115 104 5 40 50 60 70 80 90 95 75 7 35 45 55 60 70 75 80 60 10 35 40 45 50 55 60 c extal-xtal (pf) 47pf 39pf 33pf 27pf 22pf 18pf 13pf 10pf maximum esr vs. extal?xtal capacitor value, 10mhz resonators shunt capacitance (pf) (vddpll=0) 3 25 35 40 50 55 65 70 70 5 25 30 35 40 50 55 60 7 20 25 30 35 40 45 10 15 20 25 30 35 c extal-xtal (pf) 47pf 39pf 33pf 27pf 22pf 18pf 13pf 10pf maximum esr vs. extal?xtal capacitor value, 16mhz resonators shunt capacitance (pf) (1) (vddpll=0) 3 5 7 10 c extal-xtal (pf) 47pf 39pf 33pf 27pf 22pf 18pf 13pf 10pf = not allowed 1. please refer to point 1 in 12.4.3.1 how to use this information for important information regarding shunt ca- pacitance.
oscillator mc68hc912d60c colpitts oscillator specification mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor oscillator 191 12.4.4 mc68hc912d60c dc blocking ca pacitor guidelines due to the placement of the res onator from extal to vss and the nature of the microcontrolle r?s inputs, there will be a dc bias voltage of approximately (vdd?2v) ac ross the pins of the resonator. for some resonators, this can hav e long-term reliability i ssues. to remedy this situation, a dc-blocking capacitor can be plac ed in series with the crystal, as shown in figure 12-3 . the value of the dc-blocking capac itor should be between 0.1 and 10nf, with a preferred valu e of 1nf. this capaci tor must be connected as shown in figure 12-3 . if connected thus, all other oscillator specifications and guidel ines continue to apply.
oscillator technical data mc68hc9 12d60a ? rev. 3.1 192 oscillator freesca le semiconductor figure 12-3. mc68hc912d60c crystal with dc blocking capacitor alc + - ota + - cflt rflt en bias resonator c x-ex c x-vss buf rflt cflt 2 gm extal xtal resd c dc 1nf dc- b locking ca p acito r
oscillator mc68hc912d60c colpitts oscillator specification mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor oscillator 193 12.4.5 mc68hc912d60c oscillator design guidelines proper and robust operation of the o scillator circuit requires excellent board layout design practice. poor la yout of the appl ication board can contribute to emc susceptibility, noise generation, slow starting oscillators, and reaction to noise on the clock input buff er. in addition to published errata for the mc68hc912d 60a, the following guidelines must be followed or fail ure in operation may occur. minimize capacitance to vss on extal pin ? the colpitts oscillator architecture is sensitiv e to capacitance in parallel with the resonator (from extal to vss). follow these techniques: i. remove ground plane from all layers around resonator and extal route ii. observe a minimum spacing fr om the extal trace to all other traces of at least three times the design rule minimum (until the mi crocontroller?s pin pitch prohibits this guideline) iii. where possible, use xtal as a shield between extal and vss iv. keep extal capacitanc e to less than 1pf (2pf absolute maximum) shield all oscillator com ponents from all noisy traces (while observing above guideline). keep the vsspll pin and the vss reference to the oscillator as identical as possible . impedance between these signals must be minimum. observe best pract ice supply bypassing on all mcu power pins. the oscillator?s supply reference is vdd, not vddpll. account for xtal ? vss and extal ? xtal parasitics in component values. the specified compon ent values assume a maximum parasitic ca pacitance of 1pf and 0.1pf, respectively. note: an increase in the extal?xtal para sitic as a resu lt of reducing extal?vss parasitic is acceptab le provided component value is reduced by the appr opriate value.
oscillator technical data mc68hc9 12d60a ? rev. 3.1 194 oscillator freesca le semiconductor minimize xtal and extal routing lengths to reduce emc issues. note: extal and xtal routing resistan ces are less important than capacitances. using minimum width tr aces is an acceptable trade-off to reduce capacitance. 12.5 mc68hc912d60p pierce oscillator specification this section applies to t he 3l02h mask set, whic h refers to the newest set of cgm improvements (to the mc68hc912d60a) wit h the pierce oscillator configuration enabled. the name for these devices is mc68hc912d60p. 12.5.1 mc68hc912d60p oscillator design architecture the pierce oscillator arch itecture is shown in figure 12-4 . the component configuration for this oscillator is diffe rent to all previous mc68hc912d60a configurations and the recommended components may be different. please note carefully the connection of external capacitors and the resonator in this diagram.
oscillator mc68hc912d60p pierce o scillator specification mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor oscillator 195 figure 12-4. mc68hc912d60p pier ce oscillator architecture there are the following primary di fferences between the previous colpitts (?a?) and new pierce ( ?p?) oscillator configurations: oscillator architecture was cha nged from colpitts to pierce. hysteresis was added to the clock in put buffer to reduce sensitivity to noise. the bias current to the amplifie r was optimized for less process variation. alc + - ota + - rfeedback en bias resonator c ex-vss c x-vss buf rflt cflt 2 gm extal xtal resd
oscillator technical data mc68hc9 12d60a ? rev. 3.1 196 oscillator freesca le semiconductor the input esd resistor from extal to the gate of the oscillator amplifier was changed to provi de a parallel path, reducing parasitic phase shift in the oscillator. 12.5.1.1 oscillator architecture change from colpitts to pierce the primary difference from the ?a ? to the ?p? versions of the mc68hc912d60 is the architecture, or configuration, of the oscillator. the previous version (?a?) is connected in colpitts configuration, where the resonator is connected bet ween the extal pin and vss. this configuration causes the relatively large parasitics fr om extal to vss react in parallel with the resonator , decreasing gain margin in some corners. the pierce c onfiguration places the much-lower extal to xtal parasitic capacitances in para llel with the reso nator, providing a much larger gain margin across process, temperature and voltage variance. implementation of the pie rce architecture requir ed the replacement of the previous p-type, non -inverting source-follo wer amplifier with an n- type, inverting, traditional amplifie r. additionally, t he extal biasing circuit on the colpitts configurat ions was replaced with a feedback resistor from xtal to extal to achieve self-bias. parametric differences from the ?a? to the ?p? versions of the oscillator include: phase shift from extal to xt al ? the phase shift on the ?p? version will be approxim ately 180 degrees ( vs. approximately 0 degrees on the ?a? vers ion) due to the require ment of an inverting amplifier in the pierce configuration). dc offset of oscillation on ex tal and xtal ? the dc offset of the extal and xtal nodes on the ?p? version will be approximately 0.7?1.0v ( vs. approximately vdd?2v and vdd?1v, respectively, on the ?a? ve rsion) due to the different bias requirements of the n- type inverting amplifier. amplitude of oscill ation ? the amplitude of oscillation may be slightly lower on the ?p? versio n than the ?a? vers ion due to using the same amplitude level control (alc ) circuit for both architectures. the ci rcuit responds slightly differently to the different dc offsets in the two arch itectures, resulting in slightly
oscillator mc68hc912d60p pierce o scillator specification mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor oscillator 197 lower amplitude for the pierce. the amplitude will still be sufficient for robust operation across pr ocess, temperature, and voltage variance. 12.5.1.2 clock bu ffer hysteresis the input clock buffer uses an oper ational transconductance amplifier (labeled ?ota? in the figure above) followed by a di gital buffer to amplify the input signal on the extal pin into a full-swing clo ck for use by the clock generation section of the microcontroller. ther e is an internal r-c filter (composed of co mponents rflt2 and cflt2 in the figure above), which creates the dc value to whic h the extal signal is compared. in this manner, the clock input buffer can track ch anges in the extal dc offset voltage due to process variatio n as well as external factors such as leakage. because the purpose of the clock input buffer is to amplify relatively low- swing signals into a full-r ail output, the gain of t he ota is very high. in the configuration shown, this means t hat very small levels of noise can be coupled onto the i nput of the clock buffe r resulting in noise amplification. to remedy this issue, hysteresis was added to the ota so that the circuit could still provide the tolerance to leakage and the high gain required without the noise sensit ivity. approximately 150m v of hysteresis was added with a maximum hysteresis over process variation of 350mv. as such, the clock input buffe r will not respond to input signals until they exceed the hysteresis level. at th is point, the inpu t signal due to oscillation will dominate the total input waveform and narrow clock pulses due to noise will be eliminated. this circuit will limit the overall performance of the oscillator block only in cases where the amplitude of os cillation is less than the level of hysteresis. the minimum amplitude of o scillation is expected to be in excess of 750mv and the maximum hyst eresis is expected to be less than 350mv, providing a factor of safety in excess of two.
oscillator technical data mc68hc9 12d60a ? rev. 3.1 198 oscillator freesca le semiconductor 12.5.1.3 bias curren t process optimization for proper oscillation, the gain margin of the oscillator must exceed one or the circuit wil l not oscillate. process variance in the bias current (which controls the gain of the amplifier) can cause the gain margin to be much lower than typical. this can be as a resu lt of either too much or too little current. to reduce the process sensitivity of t he gain, the material of the device that sets the bias current was changed to a material with tighter process and temperature control. as a result, the tran sconductance and ibias variances are more limited than in the pr evious design. 12.5.1.4 input esd resist or path modification to satisfy the condition of oscillation, the oscillator circ uit must not only provide the correct amount of gain but also the correct amount of phase shift. in the pierce conf iguration, the pha se shift due to parasitics in the input path to the gate of the transc onductance amplifier must be as low as possible. in the origi nal configuration, the par asitic capacitance of the clock input buffer (ota), automatic loop control circuit (alc), and input resistor (rflt) reacted with the input resistance to cause a large phase shift. to reduce the phase shift, the input esd resi stor (marked resd in the figure above) was changed from a single path to the input circuitry (the alc and the ota) and oscillator tr ansconductance amplifier (marked gm in the figure above) to a parallel path. in this configuration, the only capacitance causing a phase shift on t he input to the transconductance device is due to the transc onductance device itself.
oscillator mc68hc912d60p pierce o scillator specification mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor oscillator 199 12.5.2 mc68hc912d60p oscillator circuit specifications 12.5.2.1 negative resistance margin negative resistance marg in (nrm) is a figure of merit commonly used to qualify an oscillator ci rcuit with a given resona tor. nrm is an indicator of how much additional resistance in series with the resonator is tolerable while still maintaining oscilla tion. this figure is usually expected to be a multiple of the nominal "maximum" rate d esr of the resonator to allow for variation and degr adation of the resonator. currently, many systems are optimiz ed for nrm by ad justing the load capacitors until nrm is maximized. this method may not achieve the best overall nrm because the optimiz ation method is empirical and not analytical. that is, the method only achieves the best nrm for the particular sample set of microcontrollers, res onators, and board values tested. the figure below shows the anticipated nr m for a nominal 4mhz resonator given the expected proce ss variance of the microcontroller (d60a), board, and crystal (excluding es r). in this case, the value of load capacitors providing the optim um nrm for a best- case situation yield an unacceptable nr m for a worst-case sit uation (the slope of the nrm vs. capacitance curve is very steep, indicating severe sensitivity to small variations). if the nrm opt imization happened to be performed on a best-case sample set, there coul d be unexpected sensitivity at worst- case. negative resistance margin vs. capacitance 10 100 1000 68 56 47 39 33 27 22 18 15 13 10 8 capacitance negative resistance margin wcs ty p ty p bcs
oscillator technical data mc68hc9 12d60a ? rev. 3.1 200 oscillator freesca le semiconductor nrm measurement techni ques can also generat e misleading results when applied to automati c level control (alc) st yle oscillator circuits such as the d60x/dx128x. many nr m methods slowly increase series resistance until oscillation stops. al c-style oscillators reduce the gain of the oscillator circui t after start-up to reduce curr ent, so if the oscillator tends to have more gain than optimum it will be more tolerant of additional resistance after start-up than it will during the start-up process. this means that nrm figures may be optimistic unless the method verifies the nrm value by attempting to start the oscillator with the additional resistance in-place. wo rse, this phenomenon exaggerates the difference between best- and worst-case nrm curves. 12.5.2.2 gain margin the gain margin of the o scillator indicates the am ount the gain of the oscillator can vary while maintaini ng oscillation. s pecifically, gain margin is: gain margin = min(gain/minimum required gain, maximum allowed gain/gain) just like nrm, gain margin may be dominated by either too much or too little oscillator gain a nd an increase in gain may not increase gain margin. gain margin is theoretically related to nrm since the maximum allowed gain is (approximately) in versely proportiona l to esr, and the minimum required gain is (approximately) proporti onal to esr, leaving gain margin (approx imately) inversely proportional to esr. the preferred method for specifying th e oscillator, give n a set of load capacitor values, is to determi ne the maximum allowed esr while maintaining a worst-case gain marg in of 2. since gain margin is proportional to esr, this means the empirica lly measured nrm at the worst-case point would be approx imately twice the maximum allowed esr. however, since typical nr m is likely to be higher and most measurement techniques do not account for alc effects, actual nrm measurements are likely to be much higher.
oscillator mc68hc912d60p pierce o scillator specification mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor oscillator 201 12.5.2.3 optimizi ng component values the maximum esr possible (given a worst- case gain margin of 2) is not the optimum operat ing point. in some cases, the frequency accuracy of the oscillator is important and in other cases satisfying the traditional nrm measurement tec hnique is important. if frequency accuracy is important , the total load capacitance (the combination of the load capacitors and their a ssociated parasitics) should be equal (or close to equal) to the rat ed load capacitance of the resonator. provided the resultant load capacitors yield a maximum allowed esr greater than the maxi mum esr of the crystal (while maintaining the worst case gain marg in of 2), this is an acceptable operating point. if the maximum al lowed esr is not high enough, the closest possible components with high enough esr should be chosen. similarly, if meeting a tr aditional nrm optimization criteria is important, then the components determ ined by this method are acceptable if the same components yiel d a maximum allowed esr greater than the maximum esr of the cryst al while maintaining the worst case gain margin of 2. there is no guaran tee that component s chosen through traditional nrm optimizat ion techniques wi ll yield acceptable results across all expected variations. 12.5.2.4 key parameters the following items are of critical importance to the operation of the oscillator: extal?vss capac itor value ? the value of the component plus external (board) parasitic in excess of 1. 0pf between extal and vss. xtal?vss capacitor value ? the value of t he component plus external (board) parasitic in excess of 1.0pf bet ween xtal and vss. maximum shunt capacitance ? the maximum value of the resonator?s shunt capac itance (c0) plus t he external (board) parasitics in excess of 0.1pf from extal to xtal.
oscillator technical data mc68hc9 12d60a ? rev. 3.1 202 oscillator freesca le semiconductor vddpll setting ? the voltage applied to the vddpll pin (logic 1 means vddpll is tied to the same potential as vdd). resonator frequency ? the frequency of o scillation of the resonator. maximum esr ? the maximum effectiv e series resistance (esr) of the resonator. this figur e must include any increases due to ageing, power dissipation, temperature, process variation or particle contamination. 12.5.3 important information for calculating component values before attempting to apply the informati on in section 12.5.2.4 key parameters , the following data from the resonator vendor is required: resonator frequency (f) maximum esr (r , esr, or r1) maximum shunt capacitance (c0) load capacitance (cl) ? this is not th e external component values but rather t he capacitance applied in parallel with the resonator during th e tuning procedure. 12.5.3.1 how to use this information the following tables provide maxi mum esr vs. com ponent value for various frequencies. this table should be used in the following manner: 1. choose the set of component va lues corresponding to the correct maximum shunt c apacitance (equa l to the sum of extal?xtal parasitics in excess of 0.1pf, pl us the c0 of the resonator) and vddpll setting. 2. determine the range of compone nts for which the maximum esr is greater than the absolute maximum esr of the resonator (including ageing, power dissipat ion, temperature, process
oscillator mc68hc912d60p pierce o scillator specification mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor oscillator 203 variation or particle contamination). 3. within this range, choose the extal?vss capacitance closest to (c extal?vss = 2*cl ? 10pf). 4. if the ideal component is betw een two valid component values (the maximum esr is sufficient for both component values), then choose the component with the highest maximum esr or choose an available component betw een the two listed values. 5. choose the size of the xt al?vss capacitance equal to extal?vss capacitance. 6. if the frequency of the crystal falls between listed values, determine the appropriate com ponent for the li sted frequency values on either side and extrapolate. 7. the maximum allowed capacitor is the highest listed component, and the minimum allo wed capacitor is the lowest listed component. ?na? or ?not allowed? means t he listed component is not valid or allowed for the giv en frequency, shunt capacitance, and vddpll setting. 12.5.3.2 general specifications the following limitations apply to every system: ceramic resonators with in tegrated components must have the integrated components accounted for in th e total component value. series cut resonators should not be used. use parall el cut instead. the load capacitance should be 12pf or higher, preferably greater than 15pf.
oscillator technical data mc68hc9 12d60a ? rev. 3.1 204 oscillator freesca le semiconductor table 12-2. mc68hc912d60p extal?vss, xtal? vss capacitor val ues vs. maximum esr, shunt capacitance, and vddpll setting maximum esr vs. extal?vss or xtal?vss capacitor value, 1mhz resonators shunt capacitance (pf) (vddpll=0) 3 4400 5500 6700 8100 8500 6350 3700 2250 5 3800 4650 5400 5350 4000 2900 1650 1000 7 3300 3950 4150 3100 2300 1650 950 550 10 2700 2900 2300 1700 1200 850 500 300 c extal-vss (pf) 47pf 39pf 33pf 27pf 22pf 18pf 13pf 10pf maximum esr vs. extal?vss or xtal?vss capacitor value, 2mhz resonators shunt capacitance (pf) (vddpll=0) 3 1100 1425 1750 2200 2700 3200 3975 3925 5 975 1225 1500 1825 2150 2475 2350 1825 7 850 1050 1275 1525 1750 1925 1375 1050 10 725 875 1025 1175 1325 1050 725 550 c extal-vss (pf) 47pf 39pf 33pf 27pf 22pf 18pf 13pf 10pf maximum esr vs. extal?vss or xtal?vss capacitor value, 4mhz resonators shunt capacitance (pf) (vddpll=vdd) 3 270 350 440 560 700 850 1100 1310 5 240 310 380 470 570 680 850 970 7 210 270 320 400 480 550 670 740 10 180 220 260 320 370 420 490 520 shunt capacitance (pf) (vddpll=0) 3 250 330 410 520 660 800 1040 1230 5 230 290 350 440 540 640 800 910 7 200 250 300 370 450 520 630 700 10 170 210 250 300 350 400 450 500 c extal-vss (pf) 47pf 39pf 33pf 27pf 22pf 18pf 13pf 10pf
oscillator mc68hc912d60p pierce o scillator specification mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor oscillator 205 maximum esr vs. extal?vss or xtal?vss capacitor value, 8mhz resonators shunt capacitance (pf) (vddpll=vdd) 3 60 80 100 130 165 200 270 325 5 55 70 85 110 135 165 210 250 7 50 60 75 95 115 135 170 195 10 40 50 60 75 90 105 125 145 shunt capacitance (pf) (vddpll=0) 3 60 75 95 125 155 190 255 305 5 50 65 80 105 130 155 200 235 7 45 55 70 90 105 125 160 185 10 40 45 55 70 85 95 120 130 c extal-vss (pf) 47pf 39pf 33pf 27pf 22pf 18pf 13pf 10pf maximum esr vs. extal?vss or xtal? vss capacitor value, 10mhz resonators shunt capacitance (pf) (vddpll=0) 3 35 45 60 80 100 120 165 200 5 30 40 50 65 80 100 125 150 7 25 35 45 55 65 80 100 120 10 20 30 35 40 50 60 70 80 c extal-vss (pf) 47pf 39pf 33pf 27pf 22pf 18pf 13pf 10pf maximum esr vs. extal?vss or xtal? vss capacitor value, 16mhz resonators shunt capacitance (pf) (1) (vddpll=0) 3 10 15 20 30 35 50 60 5 10 15 20 25 30 45 7 10 15 20 30 35 10 20 c extal-vss (pf) 47pf 39pf 33pf 27pf 22pf 18pf 13pf 10pf 1. please refer to point 1 in 12.5.3.1 how to use this information for important information regarding shunt ca- pacitance.
oscillator technical data mc68hc9 12d60a ? rev. 3.1 206 oscillator freesca le semiconductor 12.5.4 mc68hc912d60p guidelines proper and robust operation of the o scillator circuit requires excellent board layout design practice. poor la yout of the appl ication board can contribute to emc susceptibility, noise generation, slow starting oscillators, and reaction to noise on the clock input buff er. in addition to published errata for the mc68hc912d 60a, the following guidelines must be followed or fail ure in operation may occur. minimize capacitance betw een extal and xtal traces ? the pierce oscillator architecture is sensitive to capacitance in parallel with the resonator (from extal to xtal). to reduce this capacitance, run a shield tr ace (connected to vss) between extal and xtal as far as possible. shield all oscillator com ponents from all noisy traces. if the vss used for shielding is not identi cal to the oscillator reference, it must be consider ed a noisy signal. keep the vsspll pin and the vss reference to the oscillator as identical as possible . impedance between these signals must be minimum. observe best pract ice supply bypassing on all mcu power pins. the oscillator?s supply reference is vdd, not vddpll. account for xtal ? vss and extal ? vss parasitics in component values. the specified compon ent values assume a maximum parasitic capacitance of 1pf for these pins. note: an increase in the extal?vss or xt al?vss parasitic as a result of reducing extal?xtal paras itic is acceptable provided the component values are reduced by the appropriate value. minimize xtal and extal routing lengths to reduce emc issues. note: extal and xtal routing resistan ces are less important than capacitances. using minimum width tr aces is an acceptable trade-off to reduce capacitance.
mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor pulse width modulator 207 technical data ? mc68hc912d60a section 13. pulse width modulator 13.1 contents 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 13.3 pwm register description . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 13.4 pwm boundary cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 13.2 introduction the pulse-width modulat or (pwm) subsystem provides four independent 8-bit pwm waveforms or two 16-bit pwm waveforms or a combination of one 16-bit and tw o 8-bit pwm waveforms. each waveform channel has a programm able period and a programmable duty-cycle as well as a dedicated counter . a flexible clock select scheme allows four different clock sources to be used with the c ounters. each of the modulators can cr eate independent, continuou s waveforms with software-selectable duty rates from 0 percent to 10 0 percent. the pwm outputs can be programmed as left-aligned out puts or center-aligned outputs. the period and duty registers are double buffered so that if they change while the channel is enabl ed, the change will not ta ke effect until the counter rolls over or the channel is disabled. if t he channel is not enabled, then writes to the period and/or duty regi ster will go directly to the latches as well as the buffer, t hus ensuring that the pwm output will always be either the old waveform or the new waveform, not some variation in between. a change in duty or period can be forced into immedi ate effect by writing the new value to the duty and/or period register s and then writing to the counter. this causes the counter to reset and the new duty and/or period values to be latched. in addition, since the counter is readable it is
pulse width modulator technical data mc68hc9 12d60a ? rev. 3.1 208 pulse width modulator freescale semiconductor possible to know where t he count is with respec t to the dut y value and software can be used to make adjus tments by turning the enable bit off and on. the four pwm channel outputs shar e general-purpose port p pins. enabling pwm pins takes precedenc e over the general -purpose port. when pwm channels are not in use, the port pins may be used for discrete input/output. figure 13-1. block diagram of pwm left-aligned output channel gate pwcntx 8-bit compare = pwdtyx 8-bit compare = pwperx up /down from port p data register to pin driver ppolx clock source (eclk or scaled eclk) (clock edge sync) reset centr = 0 mux mux s r q q pwper pwdty pwenx ppol = 0 ppol = 1 sync
pulse width modulator introduction mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor pulse width modulator 209 figure 13-2. block di agram of pwm center-a ligned output channel gate pwcntx 8-bit compare = pwdtyx 8-bit compare = pwperx reset from port p data register to pin driver ppolx clock source (eclk or scaled eclk) (clock edge sync) up /down centr = 1 mux mux t q q pwdty pwenx ppol = 1 ppol = 0 (duty cycle) (period) pwper 2 (pwper ? pwdty) 2 pwdty sync
pulse width modulator technical data mc68hc9 12d60a ? rev. 3.1 210 pulse width modulator freescale semiconductor figure 13-3. pwm clock sources 13.3 pwm register description read and write anytime. 8-bit down counter pclk2 mux pclk3 mux clock to pwm channel 2 clock to pwm channel 3 2 pwscnt1 8-bit scale register pwscal1 clock b clock s1** **clock s1 = b/2 * (pwscal1 + 1) 2 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 2 2 2 2 2 2 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 8-bit down counter pclk0 mux pclk1 mux clock to pwm channel 0 clock to pwm channel 1 2 pwscnt0 8-bit scale register pwscal0 clock a clock s0* *clock s0 = a/2 * (pwscal0 + 1) register: bits: pckb2, pckb0 pckb1, = 0 = 0 bits: pcka2, pcka0 pcka1, pwpres psbck limbdm eclk psbck is bit 0 of pwctl register. internal signal limbdm is ?1? if the mcu is in background debug mode. bit 7654321bit 0 con23 con01 pcka2 pcka1 pcka0 pckb2 pckb1 pckb0 reset: 00000000 pwclk ? pwm clocks and concatenate $0040
pulse width modulator pwm register description mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor pulse width modulator 211 con23 ? concatenate pw m channels 2 and 3 when concatenated, c hannel 2 becomes the high-orde r byte and channel 3 becomes the low-order by te. channel 2 out put pin is used as the output for this 16-bit pwm (bit 2 of por t p). channel 3 clock- select control bits determines t he clock source. channel 3 output pin becomes a general purpose i/o. 0 = channels 2 and 3 are separate 8-bit pwms. 1 = channels 2 and 3 are c oncatenated to crea te one 16-bit pwm channel. con01 ? concatenate pw m channels 0 and 1 when concatenated, c hannel 0 becomes the high-orde r byte and channel 1 becomes the low-order by te. channel 0 out put pin is used as the output for this 16-bit pwm (bit 0 of por t p). channel 1 clock- select control bits determine the clock source. channel 1 output pin becomes a general purpose i/o. 0 = channels 0 and 1 are separate 8-bit pwms. 1 = channels 0 and 1 are c oncatenated to crea te one 16-bit pwm channel. pcka2 ? pcka0 ? prescaler for clock a clock a is one of two clock sour ces which may be used for channels 0 and 1. these three bits determine the rate of clock a, as shown in table 13-1 .
pulse width modulator technical data mc68hc9 12d60a ? rev. 3.1 212 pulse width modulator freescale semiconductor pckb2 ? pckb0 ? prescaler for clock b clock b is one of two clock sour ces which may be used for channels 2 and 3. these three bits determine the rate of clock b, as shown in table 13-1 . read and write anytime. pclk3 ? pwm channel 3 clock select 0 = clock b is the clo ck source for channel 3. 1 = clock s1 is the cl ock source for channel 3. pclk2 ? pwm channel 2 clock select 0 = clock b is the clo ck source for channel 2. 1 = clock s1 is the cl ock source for channel 2. pclk1 ? pwm channel 1 clock select 0 = clock a is the clo ck source for channel 1. 1 = clock s0 is the clo ck source for channel 1. table 13-1. clock a and clock b prescaler pcka2 (pckb2) pcka1 (pckb1) pcka0 (pckb0) value of clock a (b) 000 p 001 p 2 010 p 4 011 p 8 100p 16 101p 32 110p 64 111p 128 bit 7654321bit 0 pclk3 pclk2 pclk1 pcl k0 ppol3 ppol2 ppol1 ppol0 reset: 00000000 pwpol ? pwm clock select and polarity $0041
pulse width modulator pwm register description mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor pulse width modulator 213 pclk0 ? pwm channel 0 clock select 0 = clock a is the clo ck source for channel 0. 1 = clock s0 is the clo ck source for channel 0. if a clock select is changed while a pwm signal is being generated, a truncated or stretched pulse may occur duri ng the transition. the following four bits apply in left-ali gned mode only: ppol3 ? pwm channel 3 polarity 0 = channel 3 output is low at the beginning of the period; high when the duty c ount is reached. 1 = channel 3 output is high at the beginning of the period; low when the duty c ount is reached. ppol2 ? pwm channel 2 polarity 0 = channel 2 output is low at the beginning of the period; high when the duty c ount is reached. 1 = channel 2 output is high at the beginning of the period; low when the duty c ount is reached. ppol1 ? pwm channel 1 polarity 0 = channel 1 output is low at the beginning of the period; high when the duty c ount is reached. 1 = channel 1 output is high at the beginning of the period; low when the duty c ount is reached. ppol0 ? pwm channel 0 polarity 0 = channel 0 output is low at the beginning of the period; high when the duty c ount is reached. 1 = channel 0 output is high at the beginning of the period; low when the duty c ount is reached. depending on the polarity bit, the duty register s may contain the count of either the high time or the low time. if the polar ity bit is zero and left alignment is selected, the duty regist ers contain a count of the low time. if the polarity bit is one, the duty registers cont ain a count of the high time.
pulse width modulator technical data mc68hc9 12d60a ? rev. 3.1 214 pulse width modulator freescale semiconductor setting any of the pwen x bits causes the asso ciated port p line to become an output regardless of the state of the associated data direction register (ddrp) bit. this does not change the state of the data direction bit. when pwenx returns to zero, the data direction bit controls i/o direction. on the front end of the pwm channel, the scaler clock is enabled to the pwm circuit by the pwenx enable bit being high. when all four pwm channels are disabled, the prescaler counter shuts off to save power. there is an edge-synchroni zing gate circuit to guarantee that the clock will only be enabled or disabled at an edge. read and write anytime. pwen3 ? pwm channel 3 enable the pulse modulat ed signal will be av ailable at port p, bit 3 when its clock source begins its next cycle. 0 = channel 3 is disabled. 1 = channel 3 is enabled. pwen2 ? pwm channel 2 enable the pulse modulat ed signal will be av ailable at port p, bit 2 when its clock source begins its next cycle. 0 = channel 2 is disabled. 1 = channel 2 is enabled. pwen1 ? pwm channel 1 enable the pulse modulat ed signal will be av ailable at port p, bit 1 when its clock source begins its next cycle. 0 = channel 1 is disabled. 1 = channel 1 is enabled. bit 7654321bit 0 0000pwen3pwen2pwen1pwen0 reset: 00000000 pwen ? pwm enable $0042
pulse width modulator pwm register description mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor pulse width modulator 215 pwen0 ? pwm channel 0 enable the pulse modulat ed signal will be av ailable at port p, bit 0 when its clock source begins its next cycle. 0 = channel 0 is disabled. 1 = channel 0 is enabled. pwpres is a free-running 7-bit counter. read any time. write only in special mode (smod = 1). read and write anytime. a write will cause the scaler counter pwscnt0 to load the pwscal0 value unless in special mode with discal = 1 in the pwtst register. pwm channels 0 and 1 can select clock s0 (scaled) as its input clock by setting the control bi t pclk0 and pclk1 respec tively. clock s0 is generated by dividing clock a by the va lue in the pwscal0 register + 1 and dividing again by tw o. when pwscal0 = $ff, clock a is divided by 256 then divided by two to generate clock s0. bit 7654321bit 0 0bit 654321bit 0 reset: 00000000 pwpres ? pwm prescale counter $0043 bit 7654321bit 0 bit 7654321bit 0 reset: 00000000 pwscal0 ? pwm scale register 0 $0044
pulse width modulator technical data mc68hc9 12d60a ? rev. 3.1 216 pulse width modulator freescale semiconductor pwscnt0 is a down-counter that, upon reaching $00, loads the value of pwscal0. read any time. read and write anytime. a write will cause the scaler counter pwscnt1 to load the pwscal1 value unless in special mode with discal = 1 in the pwtst register. pwm channels 2 and 3 can select clock s1 (scaled) as its input clock by setting the control bi t pclk2 and pclk3 respec tively. clock s1 is generated by dividing clock b by the va lue in the pwscal1 register + 1 and dividing again by tw o. when pwscal1 = $ff, clock b is divided by 256 then divided by two to generate clock s1. pwscnt1 is a down-counter that, upon reaching $00, loads the value of pwscal1. read any time. bit 7654321bit 0 bit 7654321bit 0 reset: 00000000 pwscnt0 ? pwm scale counter 0 value $0045 bit 7654321bit 0 bit 7654321bit 0 reset: 0 0 0 0 0 0 0 0 pwscal1 ? pwm scale register 1 $0046 bit 7654321bit 0 bit 7654321bit 0 reset: 0 0 0 0 0 0 0 0 pwscnt1 ? pwm scale counter 1 value $0047
pulse width modulator pwm register description mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor pulse width modulator 217 read and write anytime. a write will cause the pw m counter to reset to $00. in special mode, if di scr = 1, a write does no t reset the pwm counter. the pwm counters are not reset w hen pwm channels ar e disabled. the counters must be reset prior to a new enable. each counter may be read any time without affecting the count or the operation of the corresponding pwm cha nnel. writes to a counter cause the counter to be reset to $00 and fo rce an immediate load of both duty and period registers with new values . to avoid a truncated pwm period, write to a counter while the counter is disabled. in left-aligned output mode, resetting the counter and st arting the waveform output is controlled by a match be tween the period register and the value in the counter. in center-aligned output m ode the counters operate as up/down counters, where a match in period changes the counter direction. the duty register changes the state of the outpu t during the period to determine the duty. when a channel is enabled, the associated pwm counter starts at the count in the pwcntx register usin g the clock select ed for that channel. in special mode, when discp = 1 and configur ed for left-aligned output, a match of period does not rese t the associated pwm counter. bit 7654321bit 0 pwcnt0 bit 7654321bit 0 $0048 pwcnt1 bit 7654321bit 0 $0049 pwcnt2 bit 7654321bit 0 $004a pwcnt3 bit 7654321bit 0 $004b reset: 00000000 pwcntx ? pwm channel counters
pulse width modulator technical data mc68hc9 12d60a ? rev. 3.1 218 pulse width modulator freescale semiconductor read and write anytime. the value in the period register deter mines the period of the associated pwm channel. if written while the c hannel is enabled, t he new value will not take effect until the existing period terminates, forcing the counter to reset. the new period is then latched and is used until a new period value is written. reading this regi ster returns the most recent value written. to start a new period immedi ately, write the new period value and then write the counter forcing a new period to start with the new period value. period = channel-clock-period (pwper + 1) (centr = 0) period = channel-clock-period (2 pwper) (centr = 1) read and write anytime. bit 7654321bit 0 pwper0 bit 7654321bit 0 $004c pwper1 bit 7654321bit 0 $004d pwper2 bit 7654321bit 0 $004e pwper3 bit 7654321bit 0 $004f reset: 1 1 1 1 1 1 1 1 pwperx ? pwm channel period registers bit 7654321bit 0 pwdty0 bit 7654321bit 0 $0050 pwdty1 bit 7654321bit 0 $0051 pwdty2 bit 7654321bit 0 $0052 pwdty3 bit 7654321bit 0 $0053 reset: 1 1 1 1 1 1 1 1 pwdtyx ? pwm channel duty registers
pulse width modulator pwm register description mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor pulse width modulator 219 the value in each duty register det ermines the duty of the associated pwm channel. when th e duty value is equal to the counter value, the output changes state. if the register is writ ten while the channel is enabled, the new value is hel d in a buffer until the counter rolls over or the channel is disabled. reading this register re turns the most recent value written. if the duty register is greater than or equal to the value in the period register, there will be no du ty change in state. if t he duty register is set to $ff the output will alwa ys be in the state whic h would normally be the state opposite the ppolx value. left-aligned-out put mode (centr = 0): duty cycle = [(pwdtyx + 1) / (pwperx + 1)] 100% (ppolx = 1) duty cycle = [(pwperx ? pwdtyx) / (pwperx+1)] 100% (ppolx = 0) center-aligned-output mode (centr = 1): duty cycle = [(pwperx ? pwdtyx) / pwperx] 100% (ppolx = 0) duty cycle = [pwdtyx / pwperx] 100% (ppolx = 1) read and write anytime. pswai ? pwm halts while in wait mode 0 = allows pwm main clock generat or to continue while in wait mode. 1 = halt pwm main clock generator when the part is in wait mode. centr ? center-aligned output mode to avoid irregularities in the pwm output mode, writ e the centr bit only when pwm channel s are disabled. 0 = pwm channels operate in left-aligned output mode 1 = pwm channels operate in center-aligned output mode bit 7654321bit 0 0 0 0 pswai centr rdpp pupp psbck reset: 00000000 pwctl ? pwm control register $0054
pulse width modulator technical data mc68hc9 12d60a ? rev. 3.1 220 pulse width modulator freescale semiconductor rdpp ? reduced drive of port p 0 = all port p output pins have normal drive capability. 1 = all port p output pins have reduced drive capability. pupp ? pull-up port p enable 0 = all port p pins have an ac tive pull-up dev ice disabled. 1 = all port p pins have an active pull- up device enabled. psbck ? pwm stops wh ile in background mode 0 = allows pwm to conti nue while in background mode. 1 = disable pwm input clock when the part is in background mode. read anytime but write only in spec ial mode (smodn = 0). these bits are available only in special m ode and are rese t in normal mode. discr ? disable reset of channel counter on write to channel counter 0 = normal operation. write to pwm channel counter will reset channel counter. 1 = write to pwm channel counter does not reset c hannel counter. discp ? disable co mpare count period 0 = normal operation 1 = in left-aligned output mode, match of period does not reset the associated pwm counter register. discal ? disable load of scale-counters on write to the associated scale-registers 0 = normal operation 1 = write to pwscal0 and pw scal1 does not load scale counters bit 7654321bit 0 discrdiscpdiscal00000 reset: 00000000 pwtst ? pwm special mode register (?test?) $0055
pulse width modulator pwm register description mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor pulse width modulator 221 portp can be read anytime. pwm functions share port p pins 3 to 0 and take prec edence over the general-purpose port when enabled. when configured as input, a r ead will return the pin level. when configured as output, a read will return t he latched output data. a write will drive associ ated pins only if conf igured for output and the corresponding pwm channel is not enabled. after reset, all pins are general -purpose, high-i mpedance inputs. ddrp determines pin direction of po rt p when used for general-purpose i/o. read and write anytime. ddrp[7:0] ? data dire ction port p pin 7-0 0 = i/o pin configured as high impedance input 1 = i/o pin configured for output. bit 7654321bit 0 pp7 pp6 pp5 pp4 pp3 pp2 pp1 pp0 pwm ? ? ? ? pwm3 pwm2 pwm1 pwm0 reset:???????? portp ? port p data register $0056 bit 7654321bit 0 ddp7 ddp6 ddp5 ddp4 ddp3 ddp2 ddp1 ddp0 reset:00000000 ddrp ? port p data direction register $0057
pulse width modulator technical data mc68hc9 12d60a ? rev. 3.1 222 pulse width modulator freescale semiconductor 13.4 pwm boundary cases the boundary conditions fo r the pwm channel duty registers and the pwm channel period register s cause these results: table 13-2. pwm left-al igned boundary conditions pwdtyx pwperx ppolx output $ff > $00 1 low $ff > $00 0 high pwperx ? 1 high pwperx ? 0 low ? $00 1 high ?$000low table 13-3. pwm center-a ligned boundary conditions pwdtyx pwperx ppolx output $00 > $00 1 low $00 > $00 0 high pwperx ? 1 high pwperx ? 0 low ? $00 1 high ?$000low
mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor enhanced capture timer 223 technical data ? mc68hc912d60a section 14. enhanced capture timer 14.1 contents 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 14.3 enhanced capture timer modes of operation . . . . . . . . . . . . 230 14.4 timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 14.5 timer and modulus counter operation in different modes . . 261 14.2 introduction the hc12 enhanced captur e timer module has th e features of the hc12 standard timer modu le enhanced by additional features in order to enlarge the fiel d of applications, in parti cular for automotive abs applications. the additional features permi t the operation of this timer module in a mode similar to t he input control timer implemented on mc68hc11nb4. these additional f eatures are: 16-bit buffer register for f our input captur e (ic) channels. four 8-bit pulse accumulators with 8-bit buffer registers associated with the four buffered ic channels. configurable also as two 16-bit pulse accumulators. 16-bit modulus down-counter with 4-bit prescaler. four user selectable delay coun ters for input noise immunity increase. main timer prescaler extended to 7-bit.
enhanced capture timer technical data mc68hc9 12d60a ? rev. 3.1 224 enhanced capture timer freescale semiconductor this design specificati on describes the standard timer as well as the additional features. the basic timer consists of a 16-bit, software -programmable counter driven by a prescaler. this ti mer can be used for many purposes, including input waveform measur ements while simultaneously generating an output waveform. pu lse widths can vary from microseconds to many seconds. a full access for the counter regi sters or the input capture/output compare registers should take place in one clock cycle. accessing high byte and low byte separately for all of these registers may not yield the same result as acce ssing them in one word.
enhanced capture timer introduction mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor enhanced capture timer 225 figure 14-1. timer bl ock diagram in latch mode 16 bit main timer pt1 comparator tc0h hold register pt0 pt3 pt2 pt4 pt5 pt6 pt7 edg0 edg1 edg2 edg3 mux prescaler m clock 16-bit load register 16-bit modulus 0 reset edg0 edg1 edg2 edg4 edg5 edg3 edg6 edg7 1, 2, ..., 128 1, 4, 8, 16 16-bit free-running latch underflow main timer prescaler tc0 capture/compare register comparator tc1 capture/compare register comparator tc2 capture/compare register comparator tc3 capture/compare register comparator tc4 capture/compare register comparator tc5 capture/compare register comparator tc6 capture/compare register comparator tc7 capture/compare register pin logic pin logic pin logic pin logic pin logic pin logic pin logic pin logic delay counter delay counter delay counter delay counter m clock tc1h hold register tc2h hold register tc3h hold register mux mux mux pa0h hold register pac0 0 reset pa1h hold register pac1 0 reset pa2h hold register pac2 0 reset pa3h hold register pac3 write $0000 to modulus counter iclat, latq, bufen (force latch) latq (mdc latch enable) down counter
enhanced capture timer technical data mc68hc9 12d60a ? rev. 3.1 226 enhanced capture timer freescale semiconductor figure 14-2. timer block diagram in queue mode 16 bit main timer pt1 comparator tc0h hold register pt0 pt3 pt2 pt4 pt5 pt6 pt7 edg0 edg1 edg2 edg3 mux prescaler m clock 16-bit load register 16-bit modulus 0 reset edg0 edg1 edg2 edg4 edg5 edg3 edg6 edg7 1, 2, ..., 128 1, 4, 8, 16 16-bit free-running latch0 main timer prescaler tc0 capture/compare register comparator tc1 capture/compare register comparator tc2 capture/compare register comparator tc3 capture/compare register comparator tc4 capture/compare register comparator tc5 capture/compare register comparator tc6 capture/compare register comparator tc7 capture/compare register pin logic pin logic pin logic pin logic pin logic pin logic pin logic pin logic delay counter delay counter delay counter delay counter m clock tc1h hold register tc2h hold register tc3h hold register mux mux mux pa0h hold register pac0 0 reset pa1h hold register pac1 0 reset pa2h hold register pac2 0 reset pa3h hold register pac3 latch1 latch3 latch2 latq , bufen (queue mode) read tc3h hold register read tc2h hold register read tc1h hold register read tc0h hold register down counter
enhanced capture timer introduction mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor enhanced capture timer 227 figure 14-3. 8-bit pulse ac cumulators block diagram host cpu data bus pt0 load holding register and reset pulse accumulator 0 0 edg3 edg2 edg1 edg0 edge detector delay counter interrupt interrupt pt1 edge detector delay counter pt2 edge detector delay counter pt3 edge detector delay counter 8-bit pac0 (pacn0) pa0h holding register 0 8-bit pac1 (pacn1) pa1h holding register 0 8-bit pac2 (pacn2) pa2h holding register 0 8-bit pac3 (pacn3) pa3h holding register
enhanced capture timer technical data mc68hc9 12d60a ? rev. 3.1 228 enhanced capture timer freescale semiconductor figure 14-4. 16-bit pulse accumulators block diagram edge detector 8-bit pac2 intermodule bus 8-bit pac3 pt7 pt0 m clock divide by 64 clock select clk0 clk1 4:1 mux to tcnt counter paclk paclk / 256 paclk / 65536 prescaled mclk (tmsk2 bits pr2-pr0) interrupt mux (pamod) edge detector paca delay counter (pacn3) (pacn2) 8-bit pac0 8-bit pac1 interrupt pacb (pacn1) (pacn0)
enhanced capture timer introduction mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor enhanced capture timer 229 figure 14-5. block diagram fo r port7 with output compar e / pulse accumulator a figure 14-6. c3f-c0f in terrupt flag setting pulse accumulator a pad (om7=1 or ol7=1) or (oc7m7 = 1) oc7 ptn edge detector delay counter 16-bit main timer tcn input capture reg. tcnh i.c. holding reg. bufen ? latq ? tfmod set cnf interrupt
enhanced capture timer technical data mc68hc9 12d60a ? rev. 3.1 230 enhanced capture timer freescale semiconductor 14.3 enhanced capture timer modes of operation the enhanced capture timer has 8 i nput capture, output compare (ic/oc) channels same as on the hc12 standard timer (timer channels tc0 to tc7). when channels are select ed as input capture by selecting the iosx bit in tios register, they are calle d input capture (ic) channels. four ic channels are the same as on the standard timer with one capture register which memorizes the timer value captured by an action on the associated input pin. four other ic channels, in addition to the capture register, have also one buffer called holdin g register. this per mits to memorize two different timer values without gener ation of any interrupt. four 8-bit pulse accumulato rs are associated with the four buffered ic channels. each pulse accumulator has a holdin g register to memorize their value by an acti on on its external input. each pair of pulse accumulators can be used as a 16-bit pulse accumulator. the 16-bit modulus down-counter can control the transfer of the ic registers contents and the pulse accumu lators to the respective holding registers for a given period, every time th e count reaches zero. the modulus down-counter can also be used as a stand-alone time base with periodic inte rrupt capability. 14.3.1 ic channels the ic channels are com posed of four standard ic registers and four buffered ic channels. an ic register is empty when it has been read or la tched into the holding register. a holding register is empty when it has been read.
enhanced capture timer enhanced capture timer modes of operation mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor enhanced capture timer 231 14.3.1.1 non-bu ffered ic channels the main timer value is memorized in th e ic register by a valid input pin transition. if the corr esponding novwx bit of the icovw register is cleared, with a new occurrence of a c apture, the contents of ic register are overwritten by the new value. if the corresponding novwx bit of the icovw register is set, the capture register cannot be writt en unless it is empty. this will prevent the captured value to be ov erwritten until it is read. 14.3.1.2 buffered ic channels there are two modes of operations for the buffered ic channels. ic latch mode: when enabled (latq=1), the main timer value is memorized in the ic register by a valid input pin transition. the value of the buffered ic register is latched to its holding register by the modulus counter for a given period when the count reaches zero, by a write $0000 to the modulus counter or by a write to iclat in the mcctl register. if the corresponding novwx bit of the icovw regist er is cleared, with a new occurrence of a capture, the cont ents of ic register are overwritten by the new value. in case of latching, the contents of its holding register are overwritten. if the corresponding novwx bit of the icovw register is set, the capture register or its holding r egister cannot be written by an event unless they are empty (see ic channels ). this will prev ent the captured value to be overwritten until it is read or latched in the holding register. ic queue mode: when enabled (latq=0), the main timer value is memorized in the ic register by a valid input pin transition.
enhanced capture timer technical data mc68hc9 12d60a ? rev. 3.1 232 enhanced capture timer freescale semiconductor if the corresponding novwx bit of the icovw regist er is cleared, with a new occurrence of a capture, the value of the ic register will be transferred to its holding register and the ic regi ster memori zes the new timer value. if the corresponding novwx bit of the icovw register is set, the capture register or its holding r egister cannot be written by an event unless they are empty (see ic channels ). in queue mode, read s of holding regi ster will latch the corresponding pulse accumulator value to its holding register. 14.3.2 pulse accumulators there are four 8-bit pulse accumulators with four 8-bi t holding registers associated with the four ic buffe red channels. a pul se accumulator counts the number of active edge s at the input of its channel. the user can prevent 8-bit pulse accu mulators counting further than $ff by pacmx control bit in icsys ($ab). in this case a va lue of $ff means that 255 counts or more have occurred. each pair of pulse accumulators can be used as a 16-bit pulse accumulator. there are two modes of operation for the pulse accumulators. 14.3.2.1 pulse accumulator latch mode the value of the pulse accumulator is transferred to its holding register when the modulus down- counter reaches zero, a write $0000 to the modulus counter or when the force latch control bit iclat is written. at the same time the pulse accumulator is cleared. 14.3.2.2 pulse accumulator queue mode when queue mode is enabled, reads of an input capt ure holding register will transfer the contents of the a ssociated pulse accumulator to its holding register.
enhanced capture timer timer registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor enhanced capture timer 233 at the same time the pulse accumulator is cleared. 14.3.3 modulus down-counter the modulus down-counter can be used as a ti me base to generate a periodic interrupt. it can also be used to latch the values of the ic registers and the pulse accumulato rs to their holding registers. the action of latching ca n be programmed to be periodic or only once. 14.4 timer registers input/output pins default to general- purpose i/o lines un til an internal function which uses that pin is specifically ena bled. the timer overrides the state of the ddr to force the i/o state of each associated port line when an output compare using a port line is enabled. in these cases the data direction bits will hav e no affect on these lines. when a pin is assigned to output an on -chip peripheral f unction, writing to this portt bit does not affect the pin but the data is stored in an internal latch such that if the pi n becomes available for general-purpose output the driven level will be the last value writ ten to the portt bit. read or write anytime. ios[7:0] ? input capt ure or output compar e channel configuration 0 = the corresponding channel acts as an input capture 1 = the corresponding channel acts as an output compare. bit 7654321bit 0 ios7 ios6 ios5 ios4 ios3 ios2 ios1 ios0 reset:00000000 tios ? timer input capture/output compare select $0080
enhanced capture timer technical data mc68hc9 12d60a ? rev. 3.1 234 enhanced capture timer freescale semiconductor read anytime but will al ways return $00 (1 stat e is transient). write anytime. foc[7:0] ? force output co mpare action for channel 7-0 a write to this register with the corresponding data bit(s) set causes the action which is programmed for output compare ?n? to occur immediately. the action taken is the same as if a successful comparison had just taken place with the tcn register except the interrupt flag d oes not get set. read or write anytime. the bits of oc7m correspond bit-for- bit with the bits of timer port (portt). setting the oc 7mn will set the corr esponding port to be an output port regardless of the st ate of the ddrt n bit when the corresponding iosn bit is set to be an output compar e. this does not change the state of the d drt bits. at successful oc7, for each bit that is set in oc7m, the corresponding data bit oc7d is stored to the corresponding bit of the timer port. note: oc7m has priority over output acti on on the timer po rt enabled by omn and oln bits in tctl1 and tc tl2. if an oc7m bit is set, it prevents the action of corresponding om and ol bits on the se lected timer port. bit 7654321bit 0 foc7 foc6 foc5 foc4 foc3 foc2 foc1 foc0 reset: 0 0 0 0 0 0 0 0 cforc ? timer compare force register $0081 bit 7654321bit 0 oc7m7 oc7m6 oc7m5 oc7m4 oc7m3 oc7m2 oc7m1 oc7m0 reset: 0 0 0 0 0 0 0 0 oc7m ? output compare 7 mask register $0082
enhanced capture timer timer registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor enhanced capture timer 235 read or write anytime. the bits of oc7d corres pond bit-for-bit with t he bits of timer port (portt). when a successful oc7 com pare occurs, for each bit that is set in oc7m, the corresponding data bit in oc7d is stored to the corresponding bit of the timer port. when the oc7mn bit is set, a succe ssful oc7 action will override a successful oc[6:0] compare action durin g the same cycle; therefore, the ocn action taken will depend on the corresponding oc7d bit. the 16-bit main timer is an up counter. a full access for the counter register should take place in one clock cycle. a separate read/write for high byte and lo w byte will give a different result than accessing them as a word. read anytime. write has no meaning or effect in the normal mode; only writable in special modes (smodn = 0). the period of the first count after a write to the tcnt registers may be a different size because the write is not synchronized wi th the prescaler clock. bit 7654321bit 0 oc7d7 oc7d6 oc7d5 oc7d4 oc7d3 oc7d2 oc7d1 oc7d0 reset: 0 0 0 0 0 0 0 0 oc7d ? output compare 7 data register $0083 bit 7654321bit 0 bit 15 14 13 12 11 10 9 bit 8 bit 7654321bit 0 reset: 0 0 0 0 0 0 0 0 tcnt ? timer count register $0084?$0085
enhanced capture timer technical data mc68hc9 12d60a ? rev. 3.1 236 enhanced capture timer freescale semiconductor read or write anytime. ten ? timer enable 0 = disables the main timer, incl uding the counter. can be used for reducing power consumption. 1 = allows the timer to function normally. if for any reason the timer is not active, there is no 64 clock for the pulse accumulator since the e 64 is generated by the timer prescaler. tswai ? timer module stops while in wait 0 = allows the timer module to continue running during wait. 1 = disables the timer module when the mcu is in the wait mode. timer interrupts cannot be used to get the mcu out of wait. tswai also affects pulse accumu lators and modulus down counters. tsbck ? timer and modulus counte r stop while in background mode 0 = allows the timer and modulus c ounter to continue running while in background mode. 1 = disables the timer and modulus counter whenever the mcu is in background mode. this is useful for emulation. tbsck does not stop th e pulse accumulator. tffca ? timer fast flag clear all 0 = allows the timer flag clea ring to function normally. 1 = for tflg1($8e), a read from an i nput capture or a write to the output compare channel ($90?$9f) causes the corresponding channel flag, cnf, to be clear ed. for tflg2 ($8f), any access to the tcnt regist er ($84, $85) clear s the tof flag. any access to the pacn3 and pacn2 registers ($a2, $a3) clears the paovf and paif flags in the paflg register ($a1). any access to the pacn1 and pacn0 registers ($a4, $a5) clears the pbovf flag in the pbflg register ($b1). any access to the bit 7654321bit 0 ten tswai tsbck tffca reset:00000000 tscr ? timer system control register $0086
enhanced capture timer timer registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor enhanced capture timer 237 mccnt register ($b6, $b7) clears the mczf flag in the mcflg register ($a7). this ha s the advantage of eliminating software overhead in a separate clear sequence. extra care is required to avoid accidental flag clearing due to unintended accesses. read or write anytime. omn ? output mode oln ? output level these eight pairs of control bits are encoded to spec ify the output action to be taken as a result of a successf ul ocn compare. when either omn or oln is one, the pin associated with ocn becomes an output tied to ocn regardless of t he state of the associated ddrt bit. note: to enable output action by omn and o ln bits on the timer port, the corresponding bit in oc 7m should be cleared. bit 7654321bit 0 reset: 00000000 tqcr ? reserved $0087 bit 7654321bit 0 om7ol7om6ol6om5ol5om4ol4 reset:00000000 tctl1 ? timer control register 1 $0088 bit 7654321bit 0 om3 ol3 om2 ol2 om1 ol1 om0 ol0 reset:00000000 tctl2 ? timer control register 2 $0089
enhanced capture timer technical data mc68hc9 12d60a ? rev. 3.1 238 enhanced capture timer freescale semiconductor to operate the 16-bit pulse accumu lators a and b (paca and pacb) independently of input c apture or output compar e 7 and 0 respectively the user must set the corresponding bits iosn = 1, omn = 0 and oln = 0. oc7m7 or oc7m0 in the oc7m register must also be cleared. read or write anytime. edgnb, edgna ? input capture edge control these eight pairs of control bits configure the i nput capture edge detector circuits. table 14-1. compare result output action omn oln action 0 0 timer disconnected from output pin logic 0 1 toggle ocn output line 1 0 clear ocn output line to zero 1 1 set ocn output line to one bit 7654321bit 0 edg7b edg7a edg6b edg6a edg5b edg5a edg4b edg4a reset: 0 0 0 0 0 0 0 0 tctl3 ? timer control register 3 $008a bit 7654321bit 0 edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg0a reset:00000000 tctl4 ? timer control register 4 $008b table 14-2. edge detector circuit configuration edgnb edgna configuration 0 0 capture disabled 0 1 capture on rising edges only 1 0 capture on falling edges only 1 1 capture on any edge (rising or falling)
enhanced capture timer timer registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor enhanced capture timer 239 read or write anytime. the bits in tmsk1 correspond bit-for-bit with the bits in the tflg1 status register. if cleared, the corresponding flag is di sabled from causing a hardware interrupt. if set, the co rresponding flag is enabled to cause a hardware interrupt. read or write anytime. c7i?c0i ? input captur e/output compare ?x ? interrupt enable. read or write anytime. toi ? timer overflow interrupt enable 0 = interrupt inhibited 1 = hardware interrupt re quested when tof flag set pupt ? timer port pu ll-up resistor enable this enable bit controls pull-up re sistors on the time r port pins when the pins are conf igured as inputs. 0 = disable pull-up resistor function 1 = enable pull-up resistor function bit 7654321bit 0 c7i c6i c5i c4i c3i c2i c1i c0i reset: 0 0 0 0 0 0 0 0 tmsk1 ? timer interrupt mask 1 $008c bit 7654321bit 0 toi 0 pupt rdpt tcre pr2 pr1 pr0 reset: 00000000 tmsk2 ? timer interrupt mask 2 $008d
enhanced capture timer technical data mc68hc9 12d60a ? rev. 3.1 240 enhanced capture timer freescale semiconductor rdpt ? timer port drive reduction this bit reduces the effective output driver size which can reduce power supply current and gener ated noise depending upon pin loading. 0 = normal output drive capability 1 = enable output drive reduction function tcre ? timer count er reset enable this bit allows the timer counter to be reset by a successful output compare 7 event. this mode of operat ion is similar to an up-counting modulus counter. 0 = counter reset inhibi ted and counter free runs 1 = counter reset by a successful output compare 7 if tc7 = $0000 and tcre = 1, tcnt will stay at $0000 continuously. if tc7 = $ffff an d tcre = 1, tof will never be set when tcnt is reset from $ffff to $0000. pr2, pr1, pr0 ? timer prescaler select these three bits specify the number of 2 stages that are to be inserted between the module clock and the main timer counter. the newly selected prescale factor wi ll not take effect until the next synchronized edge where all presca le counter stages equal zero. table 14-3. pres caler selection pr2 pr1 pr0 prescale factor 000 1 001 2 010 4 011 8 100 16 101 32 110 64 1 1 1 128
enhanced capture timer timer registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor enhanced capture timer 241 tflg1 indicates when inte rrupt conditions have oc curred. to clear a bit in the flag register, write a one to the bit. use of the tfmod bit in the icsys r egister ($ab) in conjunction with the use of the icovw register ($aa) allo ws a timer interrupt to be generated after capturing two values in the c apture and holding r egisters instead of generating an interrupt for every capture. read anytime. write used in the cl earing mechanism (set bits cause corresponding bits to be cleared). writi ng a zero will not affect current status of the bit. when tffca bit in tscr r egister is set, a read from an input capture or a write into an output compare channel ($90?$9f) will cause the corresponding channel flag cnf to be cleared. c7f?c0f ? input capture/outp ut compare channel ?n? flag. tflg2 indicates when inte rrupt conditions have oc curred. to clear a bit in the flag register , set the bit to one. read anytime. write used in clea ring mechanism (set bits cause corresponding bits to be cleared). any access to tcnt will clear tflg2 register if the tffca bit in tscr register is set. bit 7654321bit 0 c7f c6f c5f c4f c3f c2f c1f c0f reset: 00000000 tflg1 ? main timer interrupt flag 1 $008e bit 7654321bit 0 tof0000000 reset: 00000000 tflg2 ? main timer interrupt flag 2 $008f
enhanced capture timer technical data mc68hc9 12d60a ? rev. 3.1 242 enhanced capture timer freescale semiconductor tof ? timer overflow flag set when 16-bit free-running timer overflows from $ffff to $0000. this bit is cleared automa tically by a write to the tflg2 register with bit 7 set. (see also tc re control bit explanation.) bit 7654321bit 0 bit 15 14 13 12 11 10 9 bit 8 bit 7654321bit 0 tc0 ? timer input capture/output compare register 0 $0090?$0091 bit 7654321bit 0 bit 15 14 13 12 11 10 9 bit 8 bit 7654321bit 0 tc1 ? timer input capture/output compare register 1 $0092?$0093 bit 7654321bit 0 bit 15 14 13 12 11 10 9 bit 8 bit 7654321bit 0 tc2 ? timer input capture/output compare register 2 $0094?$0095 bit 7654321bit 0 bit 15 14 13 12 11 10 9 bit 8 bit 7654321bit 0 tc3 ? timer input capture/output compare register 3 $0096?$0097 bit 7654321bit 0 bit 15 14 13 12 11 10 9 bit 8 bit 7654321bit 0 tc4 ? timer input capture/output compare register 4 $0098?$0099 bit 7654321bit 0 bit 15 14 13 12 11 10 9 bit 8 bit 7654321bit 0 tc5 ? timer input capture/output compare register 5 $009a?$009b
enhanced capture timer timer registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor enhanced capture timer 243 depending on the tios bit fo r the correspondi ng channel, these registers are used to la tch the value of the fr ee-running counter when a defined transition is sensed by the corresponding input capture edge detector or to trigger an out put action for output compare. read anytime. write anyti me for output compare function. writes to these registers have no meaning or effect during input capture. all timer input capture/output compar e registers are reset to $0000. 16-bit pulse accumulator a (paca) is formed by cascading the 8-bit pulse accumulators pac3 and pac2. when paen is set, the p aca is enabled. the paca shares the input pin with ic7. read: any time write: any time bit 7654321bit 0 bit 15 14 13 12 11 10 9 bit 8 bit 7654321bit 0 tc6 ? timer input capture/output compare register 6 $009c?$009d bit 7654321bit 0 bit 15 14 13 12 11 10 9 bit 8 bit 7654321bit 0 tc7 ? timer input capture/output compare register 7 $009e?$009f bit 7654321bit 0 0 paen pamod pedge clk1 clk0 paovi pai reset: 00000000 pactl ? 16-bit pulse accumulator a control register $00a0
enhanced capture timer technical data mc68hc9 12d60a ? rev. 3.1 244 enhanced capture timer freescale semiconductor paen ? pulse accumulator a system enable 0 = 16-bit pulse accumulator a system disabled. 8-bit pac3 and pac2 can be enabled when t heir related e nable bits in icpacr ($a8) are set. pulse accumulator input edge flag (paif) function is disabled. 1 = pulse accumulator a system enabled. the tw o 8-bit pulse accumulators pac3 and pac2 are cascaded to form the paca 16-bit pulse accumulator. when paca in enabled, the pacn3 and pacn2 registers cont ents are respectively the high and low by te of the paca. pa3en and pa2en control bits in icpacr ($a8 ) have no effect. pulse accumulator input edge fl ag (paif) functi on is enabled. paen is independent from ten. with timer disabled, the pulse accumulator can still function unless pulse a ccumulator is disabled. pamod ? pulse accumulator mode 0 = event counter mode 1 = gated time accumulation mode pedge ? pulse accumulator edge control for pamod bit = 0 (event counter mode). 0 = falling edges on pt7 pin caus e the count to be incremented 1 = rising edges on pt7 pin cause the count to be incremented for pamod bit = 1 (gated ti me accumulation mode). 0 = pt7 input pin hi gh enables m divided by 64 clock to pulse accumulator and the trailing fall ing edge on pt7 sets the paif flag. 1 = pt7 input pin low enables m divided by 64 clock to pulse accumulator and the trailing ri sing edge on pt7 sets the paif flag. pamod pedge pin action 0 0 falling edge 0 1 rising edge 1 0 div. by 64 clock enabled with pin high level 1 1 div. by 64 clock enabled with pin low level
enhanced capture timer timer registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor enhanced capture timer 245 if the timer is not active (ten = 0 in tscr), there is no divide-by-64 since the e 64 clock is generated by the timer prescaler. clk1, clk0 ? clock select bits if the pulse accumulator is disabl ed (paen = 0), the prescaler clock from the timer is alwa ys used as an input clo ck to the timer counter. the change from one selected clock to the other happens immediately after thes e bits are written. paovi ? pulse accumulator a overflow interrupt enable 0 = interrupt inhibited 1 = interrupt requeste d if paovf is set pai ? pulse accumulator i nput interrupt enable 0 = interrupt inhibited 1 = interrupt reques ted if paif is set read or write anytime. w hen the tffca bit in the t scr register is set, any access to the pacnt r egister will clear all the flags in the paflg register. paovf ? pulse accumulator a overflow flag set when the 16-bit pulse accumu lator a overflows from $ffff to $0000,or when 8-bit pulse accumulato r 3 (pac3) overflows from $ff to $00. clk1 clk0 clock source 0 0 use timer prescaler clock as timer counter clock 0 1 use paclk as input to timer counter clock 1 0 use paclk/256 as timer counter clock frequency 1 1 use paclk/65536 as timer counter clock frequency bit 7654321bit 0 000000paovfpaif reset: 00000000 paflg ? pulse accumulator a flag register $00a1
enhanced capture timer technical data mc68hc9 12d60a ? rev. 3.1 246 enhanced capture timer freescale semiconductor this bit is cleared automat ically by a write to the paflg register with bit 1 set. paif ? pulse accumulator input edge flag set when the selected edge is detected at the pt7 input pin. in event mode the event edge tri ggers paif and in gated time accumulation mode the trailing edge of the gate si gnal at the pt7 i nput pin triggers paif. this bit is cleared by a write to the paflg regi ster with bit 0 set. any access to the pacn3, pacn2 regi sters will clear al l the flags in this register when tffca bit in register tscr($86) is set. read: any time write: any time the two 8-bit pulse accumulators p ac3 and pac2 are cascaded to form the paca 16-bit pulse accumulator. when paca in enabled (paen=1 in pactl, $a0) the pacn3 and pacn2 registers contents are respectively the high and low byte of the paca. when pacn3 overflows from $ff to $00, the interrupt flag paovf in paflg ($a1) is set. full count register access should take place in one clock cycle. a separate read/write for high byte and low byte will gi ve a different result than accessing them as a word. bit 7654321bit 0 $00a2 bit 7 6 5 4 3 2 1 bit 0 pacn3 (hi) $00a3 bit 7 6 5 4 3 2 1 bit 0 pacn2 (lo) reset: 00000000 pacn3, pacn2 ? pulse accumulato rs count registers $00a2, $00a3
enhanced capture timer timer registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor enhanced capture timer 247 read: any time write: any time the two 8-bit pulse accumulators p ac1 and pac0 are cascaded to form the pacb 16-bit pulse accumulator. when pacb in enabled, (pben=1 in pbctl, $b0) the pacn1 and pacn0 registers contents are respectively the high and low byte of the pacb. when pacn1 overflows from $ff to $00, the interrupt flag pbovf in pbflg ($b1) is set. full count register access should take place in one clock cycle. a separate read/write for high byte and low byte will gi ve a different result than accessing them as a word. read: any time write: any time mczi ? modulus counter un derflow interrupt enable 0 = modulus counter interrupt is disabled. 1 = modulus counter interrupt is enabled. bit 7654321bit 0 $00a4bit 7654321bit 0pacn1 (hi) $00a5bit 7654321bit 0pacn0 (lo) reset:00000000 pacn1, pacn0 ? pulse accumulato rs count registers $00a4, $00a5 bit 7654321bit 0 mczi modmc rdmcl iclat flmc mcen mcpr1 mcpr0 reset: 00000000 mcctl ? 16-bit modulus down-c ounter control register $00a6
enhanced capture timer technical data mc68hc9 12d60a ? rev. 3.1 248 enhanced capture timer freescale semiconductor modmc ? modulus mode enable 0 = the counter counts once from the value wr itten to it and will stop at $0000. 1 = modulus mode is enabled. when the c ounter reaches $0000, the counter is loaded with the latest va lue written to the modulus count register. note: for proper operation, t he mcen bit should be cl eared before modifying the modmc bit in order to rese t the modulus c ounter to $ff. rdmcl ? read modulus down-counter load 0 = reads of the modulus count register will return the present value of the c ount register. 1 = reads of the modulus count regi ster will return the contents of the load register. iclat ? input capture for ce latch action when input capture latch mode is enabled (latq and bufen bit in icsys ($ab) are set), a write one to this bit im mediately forces the contents of the inpu t capture registers tc0 to tc3 and their corresponding 8-bit pulse accumu lators to be la tched into the associated holding registers. the pulse accumulators will be automatically cleared when the latch action occurs. writing zero to this bit has no effec t. read of this bit will return always zero. flmc ? force load register into t he modulus counter count register this bit is active on ly when the modulus down-counter is enabled (mcen=1). a write one into this bit loads the load regist er into the modulus counter count register. this al so resets the modulus counter prescaler. write zero to this bit has no effect. when modmc=0, counter starts counting and stops at $0000. read of this bit will return always zero.
enhanced capture timer timer registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor enhanced capture timer 249 mcen ? modulus down -counter enable 0 = modulus count er disabled. 1 = modulus counter is enabled. when mcen=0, the counter is preset to $ffff. this will prevent an early interrupt flag when the m odulus down-counter is enabled. mcpr1, mcpr0 ? modulus counter prescaler select these two bits specify the division rate of the modulus counter prescaler. the newly selected prescaler division ra te will not be effective until a load of the load regi ster into the modulus counter count register occurs. read: any time write: only for clearing bit 7 mczf ? modulus counter underflow interrupt flag the flag is set when the modu lus down-counter reaches $0000. writing a1 to this bit cl ears the flag (if tffca=0) . writing zero has no effect. any access to the mccnt register will clear t he mczf flag in this register when tffca bit in register tscr($86) is set. mcpr1 mcpr0 prescaler division rate 00 1 01 4 10 8 11 16 bit 7654321bit 0 mczf 0 0 0 polf3 polf2 polf1 polf0 reset: 0 0 0 0 0 0 0 0 mcflg ? 16-bit modulus down-counter flag register $00a7
enhanced capture timer technical data mc68hc9 12d60a ? rev. 3.1 250 enhanced capture timer freescale semiconductor polf3 ? polf0 ? first input capture polarity status these are read only bits . write to these bi ts has no effect. each status bit gives the polarity of the first edge which has caused an input capture to occur af ter capture latch has been read. each polfx corresponds to a timer portx input. 0 = the first input capture has been caused by a falling edge. 1 = the first input capture has been caused by a rising edge. the 8-bit pulse accumulators pac 3 and pac2 can be enabled only if paen in patcl ($a0) is cleared. if paen is set, pa3en and pa2en have no effect. the 8-bit pulse accumulators pac 1 and pac0 can be enabled only if pben in pbtcl ($b0) is cleared. if pben is set, pa1en and pa0en have no effect. read: any time write: any time paxen ? 8-bit pulse ac cumulator ?x? enable 0 = 8-bit pulse accumu lator is disabled. 1 = 8-bit pulse accu mulator is enabled. bit 7654321bit 0 0000pa3enpa2enpa1enpa0en reset: 00000000 icpacr ? input control pulse accumu lators control register $00a8
enhanced capture timer timer registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor enhanced capture timer 251 read: any time write: any time if enabled, after detection of a vali d edge on input captur e pin, the delay counter counts the pre-selected nu mber of m clock (module clock) cycles, then it will generate a pulse on its output. the pulse is generated only if the level of input signal, after the preset delay, is the opposite of the level before the trans ition.this will avoid re action to narrow input pulses. after counting, the counter wi ll be cleared automatically. delay between two active edges of the input signal period should be longer than the sele cted counter delay. dlyx ? delay counter select read: any time write: any time bit 7654321bit 0 000000dly1dly0 reset: 0 0 0 0 0 0 0 0 dlyct ? delay counter control register $00a9 dly1 dly0 delay 0 0 disabled (bypassed) 0 1 256 m clock cycles 1 0 512 m clock cycles 1 1 1024 m clock cycles bit 7654321bit 0 novw7 novw6 novw5 novw4 novw3 novw2 novw1 novw0 reset:00000000 icovw ? input control overwrite register $00aa
enhanced capture timer technical data mc68hc9 12d60a ? rev. 3.1 252 enhanced capture timer freescale semiconductor an ic register is empty when it has been read or latche d into the holding register. a holding register is em pty when it has been read. novwx ? no input capture overwrite 0 = the contents of the related capt ure register or holding register can be overwritten when a new in put capture or latch occurs. 1 = the related capture register or holding regi ster cannot be written by an event unless they are empty (see ic channels ). this will prevent the capt ured value to be over written until it is read or latched in th e holding register. read: any time write: may be written once (smodn=1 ). writes are always permitted when smodn=0. shxy ? share input action of input capt ure channels x and y 0 = normal operation 1 = the channel input ?x? causes t he same action on the channel ?y?. the port pin ?x? and the corresponding edge detector is used to be active on the channel ?y?. tfmod ? timer flag-setting mode use of the tfmod bit in the icsys register ($ab) in conjunction with the use of the ic ovw register ($aa) allows a timer interrupt to be generated after capturi ng two values in th e capture and holding registers instead of gen erating an interrupt for every capture. by setting tfmod in queue mode, wh en novw bit is set and the corresponding capture an d holding registers ar e emptied, an input capture event will first update the related input capture register with bit 7654321bit 0 sh37 sh26 sh15 sh04 tfmod pacmx bufen latq reset:00000000 icsys ? input control system control register $00ab
enhanced capture timer timer registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor enhanced capture timer 253 the main timer contents. at the next event the tcn data is transferred to the tcnh register , the tcn is updated and th e cnf interrupt flag is set. see figure 14-6 . in all other inpu t capture cases the interrupt flag is set by a valid external event on ptn. 0 = the timer flags c3f?c 0f in tflg1 ($8e) are set when a valid input capture transition on the corresponding port pin occurs. 1 = if in queue mode (bufen=1 and latq=0), the timer flags c3f?c0f in tflg1 ($8e) are se t only when a latch on the corresponding holding register occurs. if the queue mode is not engaged, the timer flags c3f?c0f are set the same way as for tfmod=0. pacmx ? 8-bit pulse accu mulators maximum count 0 = normal operation. when the 8-bit pulse accumulator has reached the value $ff, with t he next active edge, it will be incremented to $00. 1 = when the 8-bit pulse accumula tor has reached the value $ff, it will not be incremented fu rther. the value $f f indicates a count of 255 or more. bufen ? ic buffer enable 0 = input capture and pulse accu mulator holding registers are disabled. 1 = input capture and pulse accu mulator holding registers are enabled. the latching mode is defined by latq control bit. write one into iclat bit in mc ctl ($a6), when latq is set will produce latching of input capture and pulse accumulators registers into thei r holding registers. latq ? input control lat ch or queue mode enable the bufen control bit should be set in order to enable the ic and pulse accumulators holding regi sters. otherwise latq latching modes are disabled. write one into iclat bit in mcc tl ($a6), when latq and bufen are set will produce latching of i nput capture and pulse accumulators registers into thei r holding registers.
enhanced capture timer technical data mc68hc9 12d60a ? rev. 3.1 254 enhanced capture timer freescale semiconductor 0 = queue mode of input capture is enabled. the main timer value is memorized in the ic register by a valid input pin transition. with a new occurrence of a capture, the val ue of the ic register will be transferred to its holding register and the ic register memorizes the new timer value. 1 = latch mode is enabled. la tching function occurs when modulus down-counter r eaches zero or a zero is written into the count register mccnt (see buffered ic channels ). with a latching event the content s of ic regist ers and 8-bit pulse accumulators are transfe rred to their holding registers. 8-bit pulse accumula tors are cleared. read: any time write: only in spec ial mode (smod = 1). tcbyp ? main timer divider chain bypass 0 = normal operation 1 = for testing only. the 16-bit free- running timer count er is divided into two 8-bit halves and the prescaler is bypassed. the clock drives both halves directly. when the high byte of timer c ounter tcnt ($84) overflows from $ff to $00, the tof flag in tflg 2 ($8f) will be set. bit 7654321bit 0 000000tcbyp0 reset:00000000 timtst ? timer test register $00ad
enhanced capture timer timer registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor enhanced capture timer 255 read: any time (inputs return pin leve l; outputs return data register contents) write: data stored in an internal latch (drives pi ns only if configured for output) since the output compar e 7 shares the pin wi th pulse accumulator input, the only way for pulse ac cumulator to receive an independent input from output compare 7 is se tting both om7 & ol7 to be zero, and also oc7m7 in oc7m register to be zero. oc7 is still able to reset the counter if enabled while pt7 is used as input to pulse accumulator. portt can be read anytime. when conf igured as an i nput, a read will return the pin level. w hen configured as an output, a read will return the latched output data. note: writes do not change pin state when the pin is configured for timer output. the minimum pulse width for pulse accumulator input should always be greater than the width of two modul e clocks due to input synchronizer circuitry. the minimum pulse width for the input capture should always be greater than the width of tw o module clocks due to input synchronizer circuitry. bit 7654321bit 0 port pt7 pt6 pt5 pt4 pt3 pt2 pt1 pt0 timer i/oc7 i/oc6 i/oc5 i/oc4 i/oc3 i/oc2 i/oc1 i/oc0 reset:00000000 portt ? timer port data register $00ae
enhanced capture timer technical data mc68hc9 12d60a ? rev. 3.1 256 enhanced capture timer freescale semiconductor read or write any time. 0 = configures the corres ponding i/o pin for input only 1 = configures the corr esponding i/o pin for output. the timer forces the i/o state to be an output for each timer port line associated with an enabled output comp are. in these cases the data direction bits will not be changed, but have no effect on the direction of these pins. the ddrt will revert to controll ing the i/o direction of a pin when the associated timer ou tput compare is disabled. input captures do not overri de the ddrt settings. read: any time write: any time 16-bit pulse accumulator b (pacb) is formed by cascading the 8-bit pulse accumulators pac1 and pac0. when pben is set, the pacb is enabled. the pacb s hares the input pin with ic0. pben ? pulse accumulator b system enable 0 = 16-bit pulse accumulator syst em disabled. 8-bit pac1 and pac0 can be enabled when t heir related e nable bits in icpacr ($a8) are set. bit 7654321bit 0 ddt7 ddt6 ddt5 ddt4 ddt3 ddt2 ddt1 ddt0 reset: 00000000 ddrt ? data direction register for timer port $00af bit 7654321bit 0 0 pben 0000pbovi0 reset: 00000000 pbctl ? 16-bit pulse accumulator b control register $00b0
enhanced capture timer timer registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor enhanced capture timer 257 1 = pulse accumulator b system enabled. the tw o 8-bit pulse accumulators pac1 and pac0 are cascaded to form the pacb 16-bit pulse accumulator. when pacb in enabled, the pacn1 and pacn0 registers cont ents are respectively the high and low by te of the pacb. pa1en and pa0en control bits in icpacr ($a8 ) have no effect. pben is independent from ten. with timer disabled, the pulse accumulator can still function unless pulse a ccumulator is disabled. pbovi ? pulse accumulator b overflow interrupt enable 0 = interrupt inhibited 1 = interrupt requeste d if pbovf is set read: any time write: any time pbovf ? pulse accumulator b overflow flag this bit is set when t he 16-bit pulse accumula tor b overflows from $ffff to $0000, or when 8-bit puls e accumulator 1 (pac1) overflows from $ff to $00. this bit is cleared by a write to the pbflg regi ster with bit 1 set. any access to the pacn1 and pacn0 registers will cl ear the pbovf flag in this register when tffca bit in regi ster tscr($86) is set. bit 7654321bit 0 000000pbovf0 reset: 0 0 000000 pbflg ? pulse accumulator b flag register $00b1
enhanced capture timer technical data mc68hc9 12d60a ? rev. 3.1 258 enhanced capture timer freescale semiconductor read: any time write: has no effect. these registers are used to latch t he value of the co rresponding pulse accumulator when the related bits in register icpacr ($a8) are enabled (see pulse accumulators ). read: any time write: any time a full access for the counter register should take place in one clock cycle. a separate read/write for high byte and low byte will give differ ent result than accessing them as a word. if the rdmcl bit in mc ctl register is clear ed, reads of the mccnt register will return the present value of the count regist er. if the rdmcl bit is set, reads of the mccnt will return t he contents of the load register. bit 7654321bit 0 $00b2bit 7654321bit 0pa3h $00b3bit 7654321bit 0pa2h $00b4bit 7654321bit 0pa1h $00b5bit 7654321bit 0pa0h reset:00000000 pa3h?pa0h ? 8-bit pulse accumulato rs holding registers $00b2?$00b5 bit 7654321bit 0 $00b6 bit 15 14 13 12 11 10 9 bit 8 mccnth $00b7 bit 7 6 5 4 3 2 1 bit 0 mccntl reset:11111111 mccnth/l ? modulus down-counter count register $00b6, $00b7
enhanced capture timer timer registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor enhanced capture timer 259 if a $0000 is written into mccnt an d modulus counter while latq and bufen in icsys ($ab) r egister are set, the input capture and pulse accumulator registers will be latched. with a $0000 write to the mccnt, the modulus counte r will stay at zero and does not set the mczf fl ag in mcflg register. if modulus mode is enab led (modmc=1), a write to this address will update the load register with the value written to it . the count regi ster will not be updated wi th the new value until t he next counter underflow. the flmc bit in mcctl ($ a6) can be used to immediately update the count register with the new val ue if an immediat e load is desired. if modulus mode is not enabled (modmc =0), a write to this address will clear the prescaler and will immediatel y update the counter register with the value writt en to it and down-counts once to $0000.
enhanced capture timer technical data mc68hc9 12d60a ? rev. 3.1 260 enhanced capture timer freescale semiconductor read: any time write: has no effect. these registers are used to latch the value of the input capture registers tc0 ? tc3. the corresponding iosx bits in tios ($80) should be cleared (see ic channels ). bit 7654321bit 0 bit 15 14 13 12 11 10 9 bit 8 bit 7654321bit 0 tc0h ? timer input capture holding register 0 $00b8?$00b9 bit 7654321bit 0 bit 15 14 13 12 11 10 9 bit 8 bit 7654321bit 0 tc1h ? timer input capture holding register 1 $00ba?$00bb bit 7654321bit 0 bit 15 14 13 12 11 10 9 bit 8 bit 7654321bit 0 tc2h ? timer input capture holding register 2 $00bc?$00bd bit 7654321bit 0 bit 15 14 13 12 11 10 9 bit 8 bit 7654321bit 0 tc3h ? timer input capture holding register 3 $00be?$00bf
enhanced capture timer timer and modulus counter operation in different modes mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor enhanced capture timer 261 14.5 timer and modulus counte r operation in different modes stop: timer and modulus counter are off since clocks are stopped. bgdm: timer and modulus counter keep on r unning, unless tsbck (reg$86, bit5) is set to one. wait: counters keep on running, unless tswai in tscr ($86) is set to one. normal: timer and modulu s counter keep on running, unless ten in tscr($86) respectively m cen in mcctl ($a6) are cleared. ten=0: all 16-bit timer operations are stopped, can only access the registers. mcen=0: modulus c ounter is stopped. paen=1: 16-bit pulse accumulator a is active. paen=0: 8-bit pulse accumulators 3 and 2 can be enabled. (see icpacr) pben=1: 16-bit pulse accumulator b is active. pben=0: 8-bit pulse accumulato rs 1 and 0 can be enabled. (see icpacr)
enhanced capture timer technical data mc68hc9 12d60a ? rev. 3.1 262 enhanced capture timer freescale semiconductor
mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor multiple serial interface 263 technical data ? mc68hc912d60a section 15. multiple serial interface 15.1 contents 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 15.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 15.4 serial communication inte rface (sci) . . . . . . . . . . . . . . . . . . 264 15.5 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . 276 15.6 port s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 15.2 introduction the multiple serial interface (msi) module consists of three independent serial i/o sub-systems: two serial communication interfaces (sci0 and sci1) and the serial peri pheral interface (spi). ea ch serial pin shares function with the gener al-purpose port pins of port s. the sci subsystems are nrz type systems that are compatible with standard rs-232 systems. these sci systems have a new single wire operation mode which allows the unused pin to be available as general-purpose i/o. the spi subsystem, which is co mpatible with the m68hc11 spi, includes new features such as ss output and bidi rectional mode.
multiple serial interface technical data mc68hc9 12d60a ? rev. 3.1 264 multiple serial interface freescale semiconductor 15.3 block diagram figure 15-1. multiple se rial interface block diagram 15.4 serial communic ation interface (sci) two serial communication inte rfaces are available on the mc68hc912d60a. these are nrz format (one start, eight or nine data, and one stop bit) asynchronous communication systems with independent internal baud ra te generation circuitry and sci transmitters and receivers. they can be configured fo r eight or nine data bits (one of which may be designated as a parity bit, odd or even). if enabled, parity is generated in hardware for transmi tted and received data. receiver parity errors are flagged in hardwar e. the baud rate generator is based on a modulus counter, allowing flexib ility in choosing baud rates. there is a receiver wake-up fe ature, an idle line dete ct feature, a loop-back mode, and various error detection f eatures. two port pins for each sci provide the external interface fo r the transmitted data (txd) and the received data (rxd). for a faster wake-up out of wait mode by a received sci message, both sci have the capabilit y of sending a receiver interrupt, if enabled, when raf (receiver active flag) is set. for compatibility with other m68hc12 products, this feature is ac tive only in wait mode and is disabled when vddpll supply is at v ss level. ps0 ps1 ps2 ps3 ps4 ps5 ps6 ps7 sci0 sci1 spi ddrs/ioctlr port s i/o drivers msi rxd0 txd0 rxd1 txd1 miso/siso mosi/momi sck cs /ss
multiple seri al interface serial communication interface (sci) mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor multiple serial interface 265 figure 15-2. serial communi cations interf ace block diagram rx baud rate tx baud rate mclk divider 10-11 bit shift reg msb txd buffer/scxdrl txmtr control scxcr2/sci ctl 2 scxcr1/sci ctl 1 scxsr1/int status data recovery 10-11 bit shift reg txd buffer/scxdrl scxbd/select lsb rxd txd pin control / ddrs / port s wake-up logic scxcr1/sci ctl 1 scxsr1/int status scxcr2/sci ctl 2 int request logic msb lsb int request logic sci receiver sci transmitter baud rate clock to internal logic data bus parity detect parity generator
multiple serial interface technical data mc68hc9 12d60a ? rev. 3.1 266 multiple serial interface freescale semiconductor 15.4.1 data format the serial data format requir es the following conditions: an idle-line in the high state bef ore transmission or reception of a message. a start bit (logic zero), transmitt ed or received, that indicates the start of each character. data that is transmitted or receiv ed least significant bit (lsb) first. a stop bit (logic one), us ed to indicate the end of a frame. (a frame consists of a start bit, a characte r of eight or nine data bits and a stop bit.) a break is defined as the transmission or reception of a logic zero for one frame or more. this sci supports hardware par ity for transmit and receive. 15.4.2 sci baud rate generation the basis of the sci baud rate generator is a 13-bit modulus counter. this counter gives the generator the flexibilit y necessary to achieve a reasonable level of i ndependence from the c pu operating frequency and still be able to produce standard bau d rates with a minimal amount of error. the clock s ource for the generator comes from the m clock. table 15-1. baud rate generation desired sci baud rate br divisor for m = 4.0 mhz br divisor for m = 8.0 mhz 110 2273 4545 300 833 2273 600 417 833 1200 208 417 2400 104 208 4800 52 104 9600 26 52 14400 17 35 19200 13 26 38400 ? 13
multiple seri al interface serial communication interface (sci) mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor multiple serial interface 267 15.4.3 sci regist er descriptions control and data register s for the sci subsystem are described below. the memory address indica ted for each register is the default address that is in use after reset. both sci have identical control registers mapped in two blocks of eight bytes. scxbdh and scxbdl are considered together as a 16-bit baud rate control register. read any time. write sbr[12:0] anytime . low order byte must be written for change to take effect. write sbr [15:13] only in special modes. the value in sbr[12:0] determines t he baud rate of the sci. the desired baud rate is determined by the following formula: which is equivalent to: br is the value writt en to bits sbr[12:0] to establish baud rate. note: the baud rate generator is disabled until te or re bit in scxcr2 register is set for the first time af ter reset, and/or th e baud rate generator is disabled when sbr[12:0] = 0. bit 7654321bit 0 btst bspl brld sbr12 sbr11 sbr10 sbr9 sbr8 high reset: 00000000 sc0bdh/sc1bdh ? sci baud rate control register $00c0/$00c8 bit 7654321bit 0 sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 low reset: 00000100 sc0bdl/sc1bdl ? sci baud rate control register $00c1/$00c9 sci baud rate mclk 16 br -------------------- = br mclk 16 sci baud rate ----------------------------------------------- - =
multiple serial interface technical data mc68hc9 12d60a ? rev. 3.1 268 multiple serial interface freescale semiconductor btst ? reserved for test function bspl ? reserved for test function brld ? reserved fo r test function read or write anytime. loops ? sci loop mode/s ingle wire mode enable 0 = sci transmit and receiv e sections operate normally. 1 = sci receive section is disc onnected from the rxd pin and the rxd pin is available as general pur pose i/o. the receiver input is determined by the rsrc bit. the transmitter output is controlled by the associated ddrs bit. both the transmitter and the receiver must be enabled to use the lo op or the single wire mode. if the ddrs bit associ ated with the txd pin is set during the loops = 1, the txd pin outputs the sci waveform. if the ddrs bit associated with the txd pin is clear during the loops = 1, the txd pin becomes high (idle line stat e) for rsrc = 0 and high impedance for rsrc = 1. refer to table 15-2 . woms ? wired-or mode for serial pins this bit controls the two pins (txd and rxd) associat ed with the scix section. 0 = pins operate in a normal mode with both high and low drive capability. to affect the rxd bit, that bi t would have to be configured as an output (via d ds0/2) which is the single wire case when using the sci. woms bit still affects general purpose output on txd and rxd pins when sc ix is not using these pins. 1 = each pin operates in an open drain fashion if that pin is declared as an output . bit 7654321bit 0 loops woms rsrc m wake ilt pe pt reset: 00000000 sc0cr1/sc1cr1 ? sci control register 1 $00c2/$00ca
multiple seri al interface serial communication interface (sci) mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor multiple serial interface 269 rsrc ? receiver source when loops = 1, the rsrc bit det ermines the in ternal feedback path for the receiver. 0 = receiver input is connected to the transmitter inte rnally (not txd pin) 1 = receiver input is connected to the txd pin m ? mode (select character format) 0 = one start, eight data, one stop bit 1 = one start, ei ght data, ninth da ta, one stop bit wake ? wake-up by address mark/idle 0 = wake up by idle line recognition 1 = wake up by address ma rk (last data bit set) ilt ? idle line type determines which of two types of id le line detection w ill be used by the sci receiver. 0 = short idle line mode is enabled. 1 = long idle line mode is detected. in the short mode, the sci circuitr y begins counting ones in the search for the idle line conditi on immediately after the start bit. this means that the stop bit and any bits that were ones before the stop bit could be counted in that string of ones, resulting in earlier recognition of an idle line. table 15-2. loop mode functions loops rsrc ddsi(3) woms function of port s bit 1/3 0 x x x normal operations 1 0 0 0/1 loop mode without txd output(txd = high impedance) 1 0 1 1 loop mode with txd output (cmos) 1 0 1 1 loop mode with txd output (open-drain) 11 0 x single wire mode without txd output (the pin is used as receiver input only, txd = high impedance) 11 1 0 single wire mode with txd output (the output is also fed back to receiver input, cmos) 1 1 1 1 single wire mode for the receiving and transmitting(open-drain)
multiple serial interface technical data mc68hc9 12d60a ? rev. 3.1 270 multiple serial interface freescale semiconductor in the long mode, the sci circuitry does not begin counting ones in the search for the idle line condition unt il a stop bit is received. therefore, the last byte?s stop bi t and preceding ?1? bits do not affect how quickly an idle line conditi on can be detected. pe ? parity enable 0 = parity is disabled. 1 = parity is enabled. pt ? parity type if parity is enabled, this bit deter mines even or odd parity for both the receiver and t he transmitter. 0 = even parity is selected. an even number of o nes in the data character causes the parity bit to be zero and an odd number of ones causes the parity bit to be one. 1 = odd parity is se lected. an odd number of ones in the data character causes the parity bi t to be zero and an even number of ones causes the parity bit to be one. read or write anytime. tie ? transmit interrupt enable 0 = tdre interrupts disabled 1 = sci interrupt will be requested whenever the tdre status flag is set. tcie ? transmit comple te interrupt enable 0 = tc interrupts disabled 1 = sci interrupt will be requested whenever the tc status flag is set. bit 7654321bit 0 tie tcie rie ilie te re rwu sbk reset:00000000 sc0cr2/sc1cr2 ? sci control register 2 $00c3/$00cb
multiple seri al interface serial communication interface (sci) mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor multiple serial interface 271 rie ? receiver interrupt enable 0 = rdrf and or interrupts disabl ed, raf interrupt in wait mode disabled 1 = sci interrupt wil l be requested whenever the rdrf or or status flag is set, or when raf is set while in wait mode with vddpll high. ilie ? idle line interrupt enable 0 = idle interrupts disabled 1 = sci interrupt will be requested whenever t he idle status flag is set. te ? transmitter enable 0 = transmitt er disabled 1 = sci transmit logic is enabled and the txd pi n (port s bit 1/bit 3) is dedicated to the transmi tter. the te bit can be used to queue an idle preamble. re ? receiver enable 0 = receiver disabled 1 = enables the sci receive circuitry. rwu ? receiver wake-up control 0 = normal sci receiver 1 = enables the wake-up function and inhibits further receiver interrupts. normally hardwar e wakes the receiver by automatically clearing this bit. sbk ? send break 0 = break generator off 1 = generate a break code (at le ast 10 or 11 contiguous zeros). as long as sbk remains set the tr ansmitter will s end zeros. when sbk is changed to zero, the current frame of all zeros is finished before the txd line goes to the idle state. if sbk is toggled on and off, the transmitter will send only 10 (o r 11) zeros and then revert to mark idle or sending data.
multiple serial interface technical data mc68hc9 12d60a ? rev. 3.1 272 multiple serial interface freescale semiconductor the bits in these regist ers are set by various conditions in the sci hardware and are automatically cl eared by special acknowledge sequences. the receive rela ted flag bits in scxs r1 (rdrf, idle, or, nf, fe, and pf) are al l cleared by a read of the scxsr1 register followed by a read of th e transmit/receive dat a register low byte. however, only those bits which were set when scxsr1 wa s read will be cleared by the subsequent read of the transmit/rece ive data register low byte. the transmit related bits in sc xsr1 (tdre and tc ) are cleared by a read of the scxsr1 register follow ed by a write to the transmit/receive data registerl low byte. read anytime (used in auto clearing mechanism). write has no meaning or effect. tdre ? transmit data register empty flag new data will not be transmitted un less scxsr1 is read before writing to the transmit dat a register. reset sets this bit. 0 = scxdr busy 1 = any byte in the trans mit data register is tran sferred to the serial shift register so new data may now be written to the transmit data register. tc ? transmit complete flag flag is set when the transmitter is idle (no data, pr eamble, or break transmission in progress). clear by reading scxsr1 with tc set and then writing to scxdr. 0 = transmitter busy 1 = transmitt er is idle bit 7654321bit 0 tdre tc rdrf idle or nf fe pf reset: 11000000 sc0sr1/sc1sr1 ? sci status register 1 $00c4/$00cc
multiple seri al interface serial communication interface (sci) mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor multiple serial interface 273 rdrf ? receive data register full flag once cleared, idle is not set again until the rxd line has been active and becomes idle again. rdrf is set if a received character is ready to be read from scxdr. clear the rdrf flag by r eading scxsr1 with rdrf set and then reading scxdr. 0 = scxdr empty 1 = scxdr full idle ? idle line detected flag receiver idle line is detected (the receipt of a minimum of 10/11 consecutive ones). this bi t will not be set by t he idle line condition when the rwu bit is set. once clea red, idle will not be set again until after rdrf has been set (after the line has been active and becomes idle again). 0 = rxd line is idle 1 = rxd line is active or ? overrun error flag new byte is ready to be transferred from the re ceive shift register to the receive data register and the receive data register is already full (rdrf bit is set). data transfer is inhibited until this bit is cleared. 0 = no overrun 1 = overrun detected nf ? noise error flag set during the same cycle as the rdrf bit but not set in the case of an overrun (or). 0 = unanimous decision 1 = noise on a valid start bit, any of the data bi ts, or on the stop bit fe ? framing error flag set when a zero is detected where a stop bit was expec ted. clear the fe flag by reading scxsr1 with fe set and then reading scxdr. 0 = stop bit detected 1 = zero detected rather than a stop bit
multiple serial interface technical data mc68hc9 12d60a ? rev. 3.1 274 multiple serial interface freescale semiconductor pf ? parity error flag indicates if received data?s parity ma tches parity bit. this feature is active only when parity is enabled. the ty pe of parity tested for is determined by the pt (par ity type) bit in scxcr1. 0 = parity correct 1 = incorrect parity detected read anytime. write has no meaning or effect. scswai ? serial communications interface stop in wait mode 0 = sci clock operates normally. 1 = halt sci clock generat ion when in wait mode. raf ? receiver active flag this bit is controlled by the receiver front end. it is set during the rt1 time period of the start bit search. it is clear ed when an idle state is detected or when the receiver circ uitry detects a false start bit (generally due to noise or baud rate mismatch). 0 = a character is not being received 1 = a character is being received if enabled with rie = 1, raf se t generates an interrupt when vddpll is high. bit 7654321bit 0 scswai mie (1) mdl1 (1) mdl0 (1) 000raf reset:00000000 sc0sr2 ? sci status register 2 $00c5/$00cd 1. see freescale interconnect bus for descriptions of these bits.
multiple seri al interface serial communication interface (sci) mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor multiple serial interface 275 r8 ? receive bit 8 read anytime. write has no meaning or affect. this bit is the ninth se rial data bit received when the sci system is configured for nine-data-bit operation. t8 ? transmit bit 8 read or write anytime. this bit is the ninth seri al data bit transmitted when the sci system is configured for nine-data-bit operat ion. when using 9-bit data format this bit does not have to be written for each data word. the same value will be transmitt ed as the ninth bit until this bit is rewritten. r7/t7?r0/t0 ? receive/transmit data bits 7 to 0 reads access the eight bits of the read-only sci receive data register (rdr). writes access the eight bits of the write-only sci transmit data register (tdr). scxdrl:scxdrh form the 9-bit data word for the sci. if the sci is bei ng used with a 7- or 8-bi t data word, only scxdrl needs to be accessed. if a 9-bit fo rmat is used, t he upper register should be written firs t to ensure that it is tr ansferred to the transmitter shift register with the lower register. bit 7654321bit 0 r8t8000000 reset:???????? sc0drh/sc1drh ? sci data register high $00c6/$00ce bit 7654321bit 0 r7/t7r6/t6r5/t5r4/t4r3/t3r2/t2r1/t1r0/t0 reset:???????? sc0drl/sc1drl ? sci data register low $00c7/$00cf
multiple serial interface technical data mc68hc9 12d60a ? rev. 3.1 276 multiple serial interface freescale semiconductor 15.5 serial peripheral interface (spi) the serial peripheral interface allows the mc 68hc912d60a to communicate synchronously with peripheral devices and other microprocessors. the spi system in the mc68hc912d 60a can operate as a master or as a sl ave. the spi is also capable of interprocessor communications in a multiple master system. when the spi is enabled, al l pins that are defined by the configuration as inputs will be inputs regardless of the state of the ddrs bits for those pins. all pins that are defined as spi outputs will be outputs only if the ddrs bits for those pins are set. any spi output w hose corresponding ddrs bit is cleared can be used as a general-purpose input. a bidirectional serial pin is possible using t he ddrs as the direction control. 15.5.1 spi baud rate generation the e clock is input to a divider series and the re sulting spi clock rate may be selected to be e di vided by 2, 4, 8, 16, 32, 64, 128 or 256. three bits in the sp0br regist er control the spi clo ck rate. this baud rate generator is activated only when spi is in the master mode and serial transfer is taking place. ot herwise this divider is disabled to save power. 15.5.2 spi operation in the spi system t he 8-bit data register in t he master and t he 8-bit data register in the slave ar e linked to form a distribut ed 16-bit register. when a data transfer operation is performed, this 16-bi t register is serially shifted eight bit po sitions by the sck clock fr om the master so the data is effectively exchanged between the master and the slave. data written to the sp0dr register of the master becomes the output data for the slave and data read from the sp0dr register of the master after a transfer operation is the i nput data from the slave.
multiple seri al interface serial peripheral interface (spi) mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor multiple serial interface 277 figure 15-3. serial peri pheral interface block diagram a clock phase control bit (cpha) and a clock polarity control bit (cpol) in the sp0cr1 register select one of four possi ble clock formats to be used by the spi system. the cpol bi t simply selects non-inverted or inverted clock. the cpha bit is used to accommodate two fundamentally different pr otocols by shifting the clock by one half cycle or no phase shift. pin control logic 8-bit shift register read data buffer shift control logic clock logic spi control sp0sr spi status register sp0dr spi data register spif wcol modf divider select sp0br spi baud rate register 2 4 8 16 32 64 128 256 spi interrupt internal bus mcu p clock (same as e rate) s m m s m s spr2 spr1 spr0 request spie spe mstr cpol cpha lsbf lsbf pups rds swom spc0 ssoe spe clock mstr swom miso ps4 sck ps6 ss ps7 mosi ps5 sp0cr1 spi control register 1 sp0cr2 spi control register 2
multiple serial interface technical data mc68hc9 12d60a ? rev. 3.1 278 multiple serial interface freescale semiconductor figure 15-4. spi clock format 0 (cpha = 0) t l begin end sck (cpol=0) sample i change o sel ss (o) transfer sck (cpol=1) msb first (lsbf=0): lsb first (lsbf=1): msb lsb lsb msb bit 5 bit 2 bit 6 bit 1 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 change o sel ss (i) (mosi pin) (miso pin) (master only) (mosi/miso) t t if next transfer begins here for t t , t l , t l minimum 1/2 sck t i t l
multiple seri al interface serial peripheral interface (spi) mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor multiple serial interface 279 figure 15-5. spi clock format 1 (cpha = 1) 15.5.3 ss output available in mast er mode only, ss output is enabled wi th the ssoe bit in the sp0cr1 register if th e corresponding ddrs is set. the ss output pin will be connected to the ss input pin of the external slave device. the ss output automatically goes low fo r each transmission to select the external device and it goes high during each idling state to deselect external devices. t l t t for t t , t l , t l minimum 1/2 sck t i t l if next transfer begins here begin end sck (cpol=0) sample i change o sel ss (o) transfer sck (cpol=1) msb first (lsbf=0): lsb first (lsbf=1): msb lsb lsb msb bit 5 bit 2 bit 6 bit 1 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 change o sel ss (i) (mosi pin) (miso pin) (master only) (mosi/miso) table 15-3. ss output selection dds7 ssoe master mode slave mode 00ss input with modf feature ss input 01 reserved ss input 1 0 general-purpose output ss input 11 ss output ss input
multiple serial interface technical data mc68hc9 12d60a ? rev. 3.1 280 multiple serial interface freescale semiconductor 15.5.4 bidirectional mode (momi or siso) in bidirectional m ode, the spi uses only one se rial data pin for external device interface. the mstr bit decides which pin to be used. the mosi pin becomes serial data i/o (momi) pin for the master mode, and the miso pin becomes serial data i/o (siso) pin for the slave mode. the direction of each serial i/o pi n depends on the corr esponding ddrs bit. 15.5.5 register descriptions control and data register s for the spi subsystem are described below. the memory address indica ted for each register is the default address that is in use after reset. for more information refer to operating modes and resource mapping . read or write anytime. when spe=1 master mode mstr=1 slave mode mstr=0 normal mode spc0=0 swom enables open drain output. swom enables open drain output. bidirectional mode spc0=1 swom enables open drain output. ps4 becomes gpio. swom enables open drain output. ps5 becomes gpio. figure 15-6. normal m ode and bidirectional mode spi mo mi dds5 serial out serial in spi si so serial in serial out dds4 spi momi ps4 dds5 serial out serial in spi ps5 siso dds4 serial in serial out bit 7654321bit 0 spie spe swom mstr cpol cpha ssoe lsbf reset: 0 0 0 0 0 1 0 0 sp0cr1 ? spi control register 1 $00d0
multiple seri al interface serial peripheral interface (spi) mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor multiple serial interface 281 spie ? spi interrupt enable 0 = spi interrupts are inhibited 1 = hardware interrupt sequence is requested each time the spif or modf status flag is set spe ? spi system enable 0 = spi internal hardware is init ialized and spi system is in a low- power disabled state. 1 = ps[4:7] are dedicat ed to the spi function when modf is set, spe always reads zero. sp0cr1 must be written as part of a mode fault recovery sequence. swom ? port s wired-or mode controls not only spi output pins but also the gener al-purpose output pins (ps[4:7]) which are not used by spi. 0 = spi and/or ps[4:7] output buffers operate normally 1 = spi and/or ps[4:7 ] output buffers behave as open-drain outputs mstr ? spi master /slave mode select 0 = slave mode 1 = master mode cpol, cpha ? spi clock polarity, clock phase these two bits are used to specify the clock fo rmat to be used in spi operations. when the clock polarity bit is cleared and dat a is not being transferred, the sck pin of the ma ster device is lo w. when cpol is set, sck idles high. see figure 15-4 and figure 15-5 . ssoe ? slave select output enable the ss output feature is enabled only in t he master mode by asserting the ssoe and dds7. lsbf ? spi lsb first enable 0 = data is transferred mo st significant bit first 1 = data is transferred l east significant bit first
multiple serial interface technical data mc68hc9 12d60a ? rev. 3.1 282 multiple serial interface freescale semiconductor normally data is transferred most si gnificant bit first.this bit does not affect the position of the msb and lsb in the data register. reads and writes of the data register will always have msb in bit 7. read or write anytime. spswai ? serial interfa ce stop in wait mode 0 = serial interface clock operates normally 1 = halt serial interface cl ock generation in wait mode spc0 ? serial pin control 0 this bit decides serial pin configurations wi th mstr control bit. bit 7654321bit 0 0 0 0 0 0 0 spswai spc0 reset: 0 0 0 0 0 0 0 0 sp0cr2 ? spi control register 2 $00d1 pin mode spc0 (1) mstr miso (2) mosi (3) sck (4) ss (5) #1 normal 0 0 slave out slave in sck in ss in #2 1 master in master out sck out ss i/o #3 bidirectional 1 0 slave i/o gpi/o sck in ss in #4 1 gpi/o master i/o sck out ss i/o 1. the serial pin control 0 bit enables bidirectional configurations. 2. slave output is enabled if dds4 = 1, ss = 0 and mstr = 0. (#1, #3) 3. master output is enabled if dds5 = 1 and mstr = 1. (#2, #4) 4. sck output is enabled if dds 6 = 1 and mstr = 1. (#2, #4) 5. ss output is enabled if dds7 = 1, ssoe = 1 and mstr = 1. (#2, #4)
multiple seri al interface serial peripheral interface (spi) mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor multiple serial interface 283 read anytime. write anytime. at reset, e clock divi ded by 2 is selected. spr[2:0] ? spi clock ( sck) rate select bits these bits are used to spec ify the spi clock rate. read anytime. write has no meaning or effect. spif ? spi interrupt request spif is set after the eighth sck cyc le in a data tr ansfer and it is cleared by reading the sp 0sr register (with spif set) followed by an access (read or write) to the spi data register. bit 7654321bit 0 00000spr2spr1spr0 reset: 00000000 sp0br ? spi baud rate register $00d2 table 15-4. spi clock rate selection spr2 spr1 spr0 e clock divisor frequency at e clock = 4 mhz frequency at e clock = 8 mhz 0 0 0 2 2.0 mhz 4.0 mhz 0 0 1 4 1.0 mhz 2.0 mhz 0 1 0 8 500 khz 1.0 mhz 0 1 1 16 250 khz 500 khz 1 0 0 32 125 khz 250 khz 1 0 1 64 62.5 khz 125 khz 1 1 0 128 31.3 khz 62.5 khz 1 1 1 256 15.6 khz 31.3 khz bit 7654321bit 0 spif wcol 0 modf 0 0 0 0 reset:00000000 sp0sr ? spi status register $00d3
multiple serial interface technical data mc68hc9 12d60a ? rev. 3.1 284 multiple serial interface freescale semiconductor wcol ? write coll ision status flag the mcu write is disabled to av oid writing over the data being transferred. no interrupt is gener ated because the er ror status flag can be read upon completi on of the transfer that was in progress at the time of the error. automatica lly cleared by a read of the sp0sr (with wcol set) followed by an a ccess (read or write) to the sp0dr register. 0 = no write collision 1 = indicates that a serial trans fer was in progress when the mcu tried to write new data in to the sp0dr data register. modf ? spi mode error interrupt status flag this bit is set automatically by spi ha rdware if the mstr control bit is set and the slave select input pin be comes zero. this condition is not permitted in normal operati on. in the case where ddrs bit 7 is set, the ps7 pin is a general- purpose output pin or ss output pin rather than being dedicated as the ss input for the sp i system. in this special case the mode fault function is inhi bited and modf remains cleared. this flag is automaticall y cleared by a read of the sp0sr (with modf set) foll owed by a write to the sp0cr1 register. read anytime (normally only after spif flag set). wr ite anytime (see wcol write collision flag). reset does not affect this address. this 8-bit register is bo th the input and output register for spi data. reads of this register are double buffered but wr ites cause data to be written directly into the serial shif ter. in the spi syst em the 8-bit data register in the master and the 8-bit data r egister in the sl ave are linked by the mosi and miso wires to form a distributed 16-bi t register. when a data transfer operation is performed, this 16-bi t register is serially shifted eight bit po sitions by the sck clock fr om the master so the data is effectively exchanged between the master and the slav e. note that bit 7654321bit 0 bit 7654321bit 0 sp0dr ? spi data register $00d5
multiple seri al interface port s mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor multiple serial interface 285 some slave devices are very simple and either accept data from the master without retu rning data to the ma ster or pass data to the master without requiring dat a from the master. 15.6 port s in all modes, port s bits ps[7:0] can be used for either general-purpose i/o, or with the sci and spi subsystems. duri ng reset, port s pins are configured as high-impedance inputs (ddrs is cleared). read anytime (inputs retu rn pin level; outputs re turn pin driver input level). write data stored in internal latch (drives pi ns only if configured for output). writes do not ch ange pin state when pin co nfigured for spi or sci output. after reset all bits are conf igured as general-purpose inputs. port s shares function with the on-chip serial systems (spi and sci0/1). read or write anytime. after reset, all general- purpose i/o are confi gured for input only. 0 = configure the correspondi ng i/o pin for input only 1 = configure the corr esponding i/o pin for output ports ? port s data register $00d6 bit 7654321bit 0 ps7 ps6 ps5 ps4 ps3 ps2 ps1 ps0 pin function ss cs sck mosi momi miso siso txd1 rxd1 txd0 rxd0 bit 7654321bit 0 dds7 dds6 dds5 dds4 dds3 dds2 dds1 dds0 reset: 0 0 0 0 0 0 0 0 ddrs ? data direction register for port s $00d7
multiple serial interface technical data mc68hc9 12d60a ? rev. 3.1 286 multiple serial interface freescale semiconductor dds2, dds0 ? data directio n for port s bit 2 and bit 0 if the sci receiver is configur ed for two-wire sci operation, corresponding port s pins will be input regardless of the state of these bits. dds3, dds1 ? data directio n for port s bit 3 and bit 1 if the sci transmitter is confi gured for two-wire sci operation, corresponding port s pins will be output regardless of the state of these bits. dds[6:4] ? data direction for port s bits 6 through 4 if the spi is enabled and expects the corresponding port s pin to be an input, it will be an input regardless of the stat e of the ddrs bit. if the spi is enabled and ex pects the bit to be an output, it will be an output only if the ddrs bit is set. dds7 ? data direction for port s bit 7 in spi slave mode, ddrs7 has no me aning or effect; the ps7 pin is dedicated as the ss input. in spi master mode, ddrs7 determines whether ps7 is an error detect input to the spi or a general-purpose or slave select output line. note: if mode fault error occurs, bits 5, 6 and 7 are forced to zero.
multiple seri al interface port s mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor multiple serial interface 287 rdps2 ? reduce drive of port s[7:4] 0 = port s[7:4] output drivers operate normally 1 = port s[7:4] output pins have reduced drive capab ility for lower power and less noise rdps1 ? reduce drive of port s[3:2] 0 = port s[3:2] output drivers operate normally 1 = port s[3:2] output pins have reduced drive capab ility for lower power and less noise rdps0 ? reduce drive of port s[1:0] 0 = port s[1:0] output drivers operate normally 1 = port s[1:0] output pins have reduced drive capab ility for lower power and less noise pups2 ? pull-up po rt s[7:4] enable 0 = no internal pull- ups on port s[7:4] 1 = port s[7:4] input pins have an ac tive pull-up devic e. if a pin is programmed as output, the pull- up device becomes inactive. pups1 ? pull-up po rt s[3:2] enable 0 = no internal pull- ups on port s[3:2] 1 = port s[3:2] input pins have an ac tive pull-up devic e. if a pin is programmed as output, the pull- up device becomes inactive. pups0 ? pull-up po rt s[1:0] enable 0 = no internal pull- ups on port s[1:0] 1 = port s[1:0] input pins have an ac tive pull-up devic e. if a pin is programmed as output, the pull- up device becomes inactive. bit 7654321bit 0 0 rdps2 rdps1 rdps0 0 pups2 pups1 pups0 reset: 0 0 0 0 0 0 0 0 purds ? pull-up register for port s $00d9
multiple serial interface technical data mc68hc9 12d60a ? rev. 3.1 288 multiple serial interface freescale semiconductor
mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor freescale interconnect bus 289 technical data ? mc68hc912d60a section 16. freescale interconnect bus 16.1 contents 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 16.3 push-pull sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 16.4 biphase coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 16.5 message validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 16.6 interfacing to mi bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 16.7 mi bus clock rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 16.8 sci0/mi bus registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 16.2 introduction the freescale interconnect bus (mi bus) is a serial communications protocol which supports distributed real -time control efficiently and with a high degree of noise immunity, at a typi cal data transfer bit rate of 20khz. the mi bus is suitable for medium speed networks requiring very low cost multiplex wiring; only one wire is required to connect to slave devices. (1) the mi bus uses a push-pull sequence to transfer data. the master device, which in this case is t he mc68hc912d60a, sends a push field to the slave devices connected to the bus. the push field contains data plus an address that is recognized by one of the slaves. th e slave addressed returns data which the master pulls fr om the mi bus over the same wire. specific details of the message format are covered later in this section. the mcu (master) can take the bus at any time, with a start bit that 1. related information on freescale?s mi bus is contained in the following freescale publications: eb409/d ? the mi bus and product fa mily for multiplexing systems an475/d ? single wire mi bus controlling stepper motors br477/d ? smart mover ? stepper motors with integrated serial bus controller
freescale inte rconnect bus technical data mc68hc9 12d60a ? rev. 3.1 290 freescale interconnect bus freescale semiconductor violates the rules of manchester biphase encodi ng. up to eight slave devices may be addressed by the mi bus. other features of mi bus include message validation, error de tection, and default value setting. on the mc68hc912d60a t he mi bus module shares the same pins on port s as the sci0 module. data is transmitted (or ?pushed?) via the txd0 pin, and received (?pulled?) via the rx d0 pin. while data is being pushed, rxd0 will be di sconnected from the receiver circuitry. the message frame is handled automatically in har dware. the mcu register interface is similar to that for the sci. 16.3 push-pull sequence communication between the mcu and the slave device always utilizes the same frame organizati on. first, the mcu sends serial data to the selected device. this data field is called the ?push field?. at the end of the push field, the selected device autom atically sends ba ck to the mcu the data held during the push sequence. the mcu reads the serial data sent by the selected device. this data is ca lled the ?pull fiel d? and contains status information followed by the end-of-frame information from the selected device. figure 16-1. mi bus timing 10 01 1 0 234 67 5 start stop start push sync d0 d1 d2 d3 d4 a0 a1 a2 pull sync s3 s2 s1 data address nrz data end of frame push field (driven by mcu) pull field (driven by slave) message frame push (biphase coded) pull (nrz coded) new frame push-pull function time slots txd0 pin (true data) mi bus wire bit fields
freescale interconnect bus biphase coding mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor freescale interconnect bus 291 16.3.1 the push field the push field consists of a start bit, a push synchronization bit, a push data field and a push address fi eld. the start consists of three time slots having the dominant logica l state ?0?. the start marks the beginning of the message frame by violation of t he rule of the m anchester code. the push synchronization bit consists of a biphase coded ?0 ?. biphase coding will be discussed later. the push data field consists of five bits of biphase coded data. the push address consists of three bi ts of biphase coded data. data and address are written to the lower byte of the sci data register (sc0drl). the push data occupi es the lower five bits and the push address occupies the upper three bits of the register. 16.3.2 the pull field the pull field consists of a pull synchronization bi t, a pull data field and an end of frame. th e pull synchronization bit is a biphase coded ?1? and is initiated by the mcu during the time slot after the last address bit of the push field. t he pull data field consists of an nrz coded transmission, each bit taking one time sl ot. once shifted in, the pull data is stored in the lower byte of the sci data register (sc0dr l). the end-of-frame field is a square wave signal having a typical frequency of 20khz 1% tolerance (i.e. the bit rate of the push fi eld) when the data sent to the selected device is valid. 16.4 biphase coding manchester biphase l codi ng is used for the push field bits. each bit requires two time slots to encode the logic value of t he bit. this encoding allows the detection of a single error at the time slot level. bits are encoded as follows: 0 = in the first time sl ot, the logic level is se t to one, followed by a logic level zero in the second time slot. 1 = in the first time slot, the logic level is set to ze ro, followed by a logic level one in t he second time slot.
freescale inte rconnect bus technical data mc68hc9 12d60a ? rev. 3.1 292 freescale interconnect bus freescale semiconductor figure 16-2. biphase cod ing and error detection 16.5 message validation the communication between th e mcu and the selected device is valid when the mcu reads a pul l data field having corr ect codes (excluding the codes ?111? and ?000?) followed by a square wave signal, having a frequency of 20khz, contained in the end-of-frame information. an mi bus error is detected when the pull field contains the code ?111? followed by the end-of-fram e permanently tied to lo gical state ?1?. this means that the comm unication between the m cu and the selected device was not accomplished. ?0? ?1? 01234567 01234567 t biphase coded signal biphase detection noise detection abab a? b? a b a? b? ab
freescale interconnect bus message validation mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor freescale interconnect bus 293 figure 16-3. mi bus block diagram & loops woms wake + & & m ilt pe pt sc0cr1 10/11-bit tx shift register h8 l 0 7 10/11-bit rx shift register 80 7 tie te rie ilie re rwu sbk sc0cr2 tdre tc or rdrf sc0sr1 data recovery rxd0 txd0 receive buffer r8 transmit buffer t8 transmitter control receiver control sci interrupt request woms woms mie pt te sbk mie re stop start sc0bdl sc0bdh rate generator mclk rie idle ilie rdrf tc tcie tdre tie note: ? = always reads as zero flag control internal data bus rsrc ? ? ? tcie nf = not used in mi bus mode clock & scswai mdl1 mdl0 raf sc0sr2 mie
freescale inte rconnect bus technical data mc68hc9 12d60a ? rev. 3.1 294 freescale interconnect bus freescale semiconductor 16.5.1 controller detected errors there are three different mi bus erro r types which are detected by the selected slave device and are not mu tually exclusive. the mcu cannot determine which error occurred. noise error ? slave devices take two sa mples in each time slot of the biphase encoded push field. an error occurs when the two samples for each time slot ar e not the same logical level. biphase error ? slave devices receiving the push field detect the biphase code. an error occurs when the two time slot s of the biphase code do not yield a logica l exclusive-or function. field error ? a field error is detected w hen the fixed-form of the push field is violated. 16.5.2 mcu detected errors there is a fourth error that can be det ected by the mc u. this error causes the noise flag (nf) to be a sserted in the sc0sr1 register during the push field sequence. bit error ? a bit error can be detect ed by the mcu during the push field. the mi bus serial system moni tors the bus via on-chip hardware at the rxd0 pin at t he same time as sending data. a bit error is detected at that bi t time when the value monito red is differ ent from the bit value sent. 16.6 interfacing to mi bus physically the mi bus consists of only a single wire. in the example shown in figure 16-4 , only a single transistor and a few passive components are required to connect up the mc68hc912d60a for full mi bus operation.
freescale interconnect bus interfacing to mi bus mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor freescale interconnect bus 295 figure 16-4. a typical mi bus interface the transistor serves both to drive the mi bus during the push field and to protect the mcu tx pin from voltage transients generated in the wiring. without the trans istor, emi could damage th e tx pin. similarly, the input pin (rx) is protected from emi by clam ping it to the mcu supply rails with two diodes. w hen a load dump occurs, t he zener diode (18v) is switched on and hence turn s the transistor on; this generates the logic ?0? state on the mi bus. after eight time slots ( 200ms) of continuous ?0? state, all devices on the mi bus will have t heir outputs disabled. the mi bus line can take two stat es, recessive or dominant. the dominant state (?0?) is repres ented by a maximum 0.3v (v cesat of the transistor, t1). the recessive state (? 1?) is represented by 5v, through a pull-up resistor of 10k ? . the bus load depends on the number of devices on the bus. each device has a pull-up resistor of 10k ? . an external terminat ion resistor is used to stabilize the load resi stance of the bus at 600 ? . 1.2k ? +12v 18v 4.7k ? 3.9k ? 10k ? mi bus tx rx mcu v dd v dd t1 v dd v ss 10k ? 22k ?
freescale inte rconnect bus technical data mc68hc9 12d60a ? rev. 3.1 296 freescale interconnect bus freescale semiconductor 16.7 mi bus clock rate the mi bus clock rate is set via the sci baud regist ers. to use the mi bus, the mclk clock frequency th at drives the sci clock generator must be selected to matc h the minimum resolution of the mi bus logic. this is expressed by the following formula: mclk = 16 n (2 push_field_bit_ rate) = 16 n 40khz = n 640khz where ?n? is an integer a nd 20khz is the minimum pu sh field bit rate for the mi bus. values for mclk c ould be 640khz,1280khz, 1920khz, ?, n 640khz. the value ?n? is the modu lus for the mi bus baud register. mclk may be the output of the pll circ uit or it may be the extal/2 input of the mcu. refer to clock divider chains . 16.8 sci0/mi bus registers mi bus operation is controlled by the sa me group of registers as is used for the sci. however the fu nctions of some of the bits are modified when in mi bus mode. a description of t he registers, as applicable to the mi bus function, is given here. in mi bus mode, bits that have no meaning are reserved by freescale, and are not described. bit 7654321bit 0 btst bspl brld sbr12 sbr11 sbr10 sbr9 sbr8 high reset: 00000000 sc0bdh ? mi bus clock rate control register $00c0 bit 7654321bit 0 sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 low reset:00000100 sc0bdl ? mi bus clock rate control register $00c1
freescale interconnect bus sci0/mi bus registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor freescale interconnect bus 297 sc0bdh and sc0bdl are considered together as a 16-bit baud rate control register. read any time. write sbr[12:0] anytime . low order byte must be written for change to take effect. write sbr[15:13] only in special modes. the value in sbr[12:0] determines t he clock rate of the mi bus. the desired baud rate is determined by the following formula: br is the value writt en to bits sbr[12:0] to establish baud rate. note: the baud rate generator is disabled until te or re bit in sc0cr2 register is set for the first time af ter reset, and/or th e baud rate generator is disabled when sbr[12:0] = 0. btst ? reserved for test function bspl ? reserved for test function brld ? reserved fo r test function read or write anytime. woms ? wired-or mode for serial pins this bit controls the two pins (txd0 and rxd0) associated with the sc0 section. 0 = pins operate in a normal m ode with both high and low drive capability. 1 = each pin operates in an open drain fashion if that pin is declared as an output . mi bus clock rate mclk 16 br -------------------- = bit 7654321bit 0 ?woms?????pt reset: 00000000 sc0cr1 ? mi bus control register 1 $00c2
freescale inte rconnect bus technical data mc68hc9 12d60a ? rev. 3.1 298 freescale interconnect bus freescale semiconductor pt ? mi bus txd0 polarity if parity is enabled, this bit deter mines even or odd parity for both the receiver and t he transmitter. 0 = mi bus transmit pi n functions normally. 1 = mi bus transmit pin w ill send inverted data. read or write anytime. rie ? receiver interrupt enable 0 = rdrf interrupt disabled. 1 = mi bus interrupt w ill be requested whenev er the rdrf status flag is set. or does not generat e an interrupt re quest in mi bus mode. te ? transmitter enable 0 = transmitter disabled. 1 = mi bus transmit logic is enabled and the txd0 pin (port s bit 1) is dedicated to the transmitter. re ? receiver enable 0 = receiver disabled. 1 = port pin dedicated to the mi bus; the receiv er is enabled by a pull sync and is inhibi ted during a push field. sbk ? send break 0 = no action. 1 = mi transmit line is set low for 20 time slots. when an mi bus wire is held low for eight or more time slots an internal circuit on any slave device connected to the bus may reset or preset the device with default values. bit 7654321bit 0 ? ? rie ? te re ? sbk reset: 0 0 0 0 0 0 0 0 sc0cr2 ? mi bus control register 2 $00c3
freescale interconnect bus sci0/mi bus registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor freescale interconnect bus 299 the bits in these registers are set by various conditions in the mi bus hardware and are automatically cl eared by special acknowledge sequences. the receive related flag bits in sc0sr1 (rdrf, or and nf) are all cleared by a read of this register followed by a read of the transmit/receive data re gister low byte. howe ver, only those bits which were set when sc0sr1 was read will be cleared by the subsequent read of the transmit/receive data register low byte. read anytime (used in auto cl earing mechanism). write has no meaning or effect. rdrf ? receive data register full flag 0 = contents of the receiver shi ft register have not been transferred to the receiver data register. 1 = contents of the receiver serial shift register have been transferred to the rece iver data register. the eof (end-of-frame) du ring an mi bus pull-fi eld is a continuous square wave, which will result in multiple rdrfs. this may be dealt with in any of the following ways: ? by clearing the rie mask, i gnoring unneeded rdrfs, initiating a push field, waiting for tdre (1) and then clearing the rdrf ? by clearing the re bit when a pull field is complete, followed by setting the re bit after the tdre 1 flag associated with the next push field is asserted. ? by disabling the mi bus. bit 7654321bit 0 ? ? rdrf ? or nf ? ? reset:11000000 sc0sr1 ? mi bus status register 1 $00c4 1. note that tdre and tc w ill both behave in the same way as during normal sci transmissions. the mi bus will still be receiving when the tc bit becomes set, hence any queued transmission will not start until the current pull field has finished. see also register descriptions .
freescale inte rconnect bus technical data mc68hc9 12d60a ? rev. 3.1 300 freescale interconnect bus freescale semiconductor or ? bit error flag 0 = no bit error has been detected. 1 = a bit error has been detected. this bit is set when a push field bit value on the mi bus does not match the bit value that was sen t. this is known as an mi bus bit error. or does not generate an interrupt request in mi bus mode. nf ? noise error flag 0 = no noise detected. 1 = noise detected. this bit is set when noise is detected on th e receive line during an mi bus pull field. read anytime. write has no meaning or effect. scswai ? serial communications interface stop in wait mode 0 = sci clock operates normally. 1 = halt sci clock generat ion when in wait mode. mie ? freescale interface bus (mi bus) enable 0 = the sci functions normally. 1 = mi bus is enabled for this subsystem. when mie is set, the sci0 registers, bi ts and pins assume the functionality required for mi bus. mdl1, mdl0 ? mi bus delay select these bits are used to se t up the delay for the st art of the nrz receive for mi bus operation as shown (for a 20khz bit rate) in the following table. bit 7654321bit 0 scswai mie mdl1 mdl0 0 0 0 raf reset: 0 0 0 0 0000 sc0sr2 ? mi bus status register 2 $00c5
freescale interconnect bus sci0/mi bus registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor freescale interconnect bus 301 raf ? receiver active flag 0 = a character is not being received 1 = a character is being received this register forms the 8-bit data/address word for the mi push field and contains the 3-bit data word received as the mi pull field. r7t7?r0t0 ? receive/trans mit data bits 7 to 0 read: reads access the three bits of pull field data (stored in bits 3?1) of the read-only mi bus receive data register. bits [7:4, 0] are a fixed data pattern when a valid status and end-of-frame is returned. a valid status is represented by t he following data pattern: 0101 xxx1 (bits 7?0), where ?xxx? is the status. all ones in the receive data register indicate that an error occurred on the mi bus. bits are received lsb first by t he mcu, and the status bits map as shown in the above table. table 16-1. mi bus delay mdl1 mdl0 delay factor delay time (1) 1. 20khz bit rate requires 25 s (40khz) time slots. 00 1 1.5625 s (2) 2. 25 s 16 01 23.125 s 10 34.6875 s 11 46.25 s bit 7654321bit 0 r7/t7 r6/t6 r5/t5 r4/t4 r3/t3 r2/t2 r1/t1 r0/t0 pull field0101s1s2s31 push fielda2a1a0d4d3d2d1d0 reset: ???????? sc0drl ? mi bus data register low $00c7
freescale inte rconnect bus technical data mc68hc9 12d60a ? rev. 3.1 302 freescale interconnect bus freescale semiconductor write: writes access the eight bits of the write-only mi bus transmit data register. mi bus devices requir e a 5-bit data pattern followed by a 3-bit address pattern to be sent during the push field. the data pattern is mapped to the lowest five bits of the data register and the address to the highest three bits, as shown in the above table. thus mi-data[4:0] is written to sc0drl [4:0] and mi-address[ 2:0] is written to sc0drl[7:5].
mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor mscan controller 303 technical data ? mc68hc912d60a section 17. mscan controller 17.1 contents 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 17.3 external pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 17.4 message storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 17.5 identifier acceptance filter . . . . . . . . . . . . . . . . . . . . . . . . . . .310 17.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314 17.7 protocol violation protecti on. . . . . . . . . . . . . . . . . . . . . . . . . . 316 17.8 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 17.9 timer link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 17.10 clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321 17.11 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 17.12 programmer?s model of message storage . . . . . . . . . . . . . . . 325 17.13 programmer?s model of control registers . . . . . . . . . . . . . . . 330 17.2 introduction the mscan12 is the specific impl ementation of the scalable can (mscan) concept targeted for the fr eescale m68hc12 microcontroller family. the module is a communication controller implementing the can 2.0 a/b protocol as defined in the bosch specification dated september 1991. the can protocol was prim arily, but not only, de signed to be used as a vehicle serial data bus, meeting the s pecific requirements of this field:
mscan controller technical data mc68hc9 12d60a ? rev. 3.1 304 mscan controller freescale semiconductor real-time processing, re liable operation in t he emi environment of a vehicle, cost-effectivene ss and required bandwidth. mscan12 utilises an advanced buf fer arrangement resulting in a predictable real-time behav iour and simplifies th e application software. 17.3 external pins the mscan12 uses 2 external pins , 1 input (rxcan) and 1 output (txcan). the txcan output pin represents the logic level on the can: 0 is for a dominant state, an d 1 is for a recessive state. rxcan is on bit 0 of port can, txc an is on bit 1. the remaining six pins of port can (1 12tqfp version only) are cont rolled by registers in the mscan12 address space (see mscan12 port can control register (pctlcan) and mscan12 port can data direction register (ddrcan) ). a typical can system with mscan12 is shown in figure 17-1 . each can station is connected physi cally to the can bus lines through a transceiver chip. the transceiver is capable of driving the large current needed for the can and has current protection, against defective can or defective stations.
mscan controller message storage mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor mscan controller 305 figure 17-1. the can system 17.4 message storage mscan12 facilitates a sophistic ated message storage system which addresses the requirements of a br oad range of network applications. 17.4.1 background modern application layer software is built upon two fundamental assumptions: 1. any can node is ab le to send out a stream of scheduled messages without releasing th e bus between two messages. such nodes will arbitrate for the bus right af ter sending the previous message and will only release the bus when arbitration is lost. 2. the internal messa ge queue within any ca n node is organized such that if more than one messa ge is ready to be sent, the highest priority message will be sent out first. transceiver mscan12 can system can station 1 can station 2 can station n can txcan rxcan ..... controller
mscan controller technical data mc68hc9 12d60a ? rev. 3.1 306 mscan controller freescale semiconductor the above behaviour cannot be achieved with a single transmit buffer. that buffer must be rel oaded right after the pr evious message has been sent. this loading process lasts a definite am ount of time and has to be completed within the inte r-frame sequence (ifs) in order to be able to send an uninterrupted stream of messages . even if this is feasible for limited can bus sp eeds it requires that t he cpu reacts with short latencies to the transmit interrupt. a double buffer scheme w ould de-couple the re-l oading of the transmit buffers from the act ual message sending and as such reduces the reactiveness requirement s on the cpu. problems may arise if the sending of a message would be finis hed just while the cpu re-loads the second buffer, no buffer would then be ready fo r transmission and the bus would be released. at least three transmit buffers are required to meet the first of above requirements under all ci rcumstances. the mscan1 2 has three transmit buffers. the second requirement calls for some sort of internal prioritisation which the mscan12 implements wit h the local priority concept described below. 17.4.2 receive structures the received messages ar e stored in a two stage input fifo. the two message buffers ar e alternately mapped into a single memory area (see figure 17-2 ). while the background receive buffer (rxbg) is exclusively associated to the mscan12, the fo reground receive buffer (rxfg) is addressable by the cpu12. this scheme simplifies the handler software as only one address area is applic able for the receive process. both buffers have a size of 13 byte s to store the can control bits, the identifier (standard or extended) and the data cont ents (for details see programmer?s model of message storage ). the receiver full flag (rxf) in the mscan12 re ceiver flag register (crflg) (see mscan12 receiver fl ag register (crflg) ) signals the status of the foreground receive buf fer. when the buffer contains a correctly received message with matching identifier this flag is set.
mscan controller message storage mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor mscan controller 307 on reception, each message is checked to see if it passes the filter (for details see identifier acce ptance filter ) and in parallel is written into rxbg. the mscan12 copies the c ontent of rxbg into rxfg (1) , sets the rxf flag, and generates a rece ive interrupt to the cpu (2) . the user?s receive handler has to read the received message from rxfg and then reset the rxf flag in orde r to acknowledge the in terrupt and to release the foreground buffer. a new message, which can follow immediately after the ifs field of the can frame, is rece ived into rxbg. the over- writing of the background buffer is independent of t he identifier filter function. 1. only if the rxf flag is not set. 2. the receive interrupt is gener ated only if not masked. a polling scheme can be applied on rxf also.
mscan controller technical data mc68hc9 12d60a ? rev. 3.1 308 mscan controller freescale semiconductor figure 17-2. user model fo r message buffer organization when the mscan12 module is transmitting, the mscan12 receives its own messages into the background re ceive buffer, rxbg, but does not overwrite rxfg, generate a receive interrupt or a cknowledge its own messages on the can bu s. the exception to this rule is in loop-back mode (see mscan12 module control register 1 (cmcr1). ) where the mscan12 treats its own messages exactly like all other incoming messages. the mscan12 re ceives its own transm itted messages in the event that it loses arbitr ation. if arbitration is lost, the mscan12 must be prepared to become receiver. rxfg rxbg tx0 rxf txe prio tx1 txe prio tx2 txe prio mscan12 cpu bus
mscan controller message storage mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor mscan controller 309 an overrun condition occurs wh en both the fo reground and the background receive message buffers ar e filled with correctly received messages with accept ed identifiers and another message is correctly received from the bus with an accepted identifier. the latter message is discarded and an error interrupt with overrun indication is generated if enabled. the mscan12 is st ill able to transmit messages with both receive message buffer s filled, but all incoming messages are discarded. 17.4.3 transmit structures the mscan12 has a triple transmit buf fer scheme in order to allow multiple messages to be set up in advance and to achieve an optimized real-time performance. the three bu ffers are arranged as shown in figure 17-2 . all three buffers have a 13 byte data st ructure similar to the outline of the receive buffers (see programmer?s model of message storage ). an additional transmit buffer priority regi ster (tbpr) contai ns an 8-bit so called local priority field (prio) (see transmit buffer priority registers (tbpr) ). in order to trans mit a message, the cpu12 has to identify an available transmit buffer which is indicated by a set tr ansmit buffer empty (txe) flag in the mscan12 transmitter flag register (ctflg) (see mscan12 transmitter flag register (ctflg) ). the cpu12 then stores the identifier, the cont rol bits and the data content into one of the transmit buffers. finally, the buffer has to be flagged as being ready for transmission by clearing the txe flag. the mscan12 will then schedule the message fo r transmission and will signal the successful tran smission of the buffer by setting the txe flag. a transmit interrupt will be emitted (1) when txe is set and this can be used to drive the ap plication software to re-load the buffer. 1. the transmit interrupt is generated only if not masked. a polling scheme can be applied on txe also.
mscan controller technical data mc68hc9 12d60a ? rev. 3.1 310 mscan controller freescale semiconductor if more than one buffer is scheduled for transmi ssion when the can bus becomes available for arbi tration, the mscan12 us es the local priority setting of the three buffers for prio ritisation. for this purpose every transmit buffer has an 8-bit local pr iority field (prio). the application software sets this field when the message is set up. the local priority reflects the priority of this partic ular message relati ve to the set of messages being emitted fr om this node. the lowest binary value of the prio field is defined to be the highest priority. the internal scheduling process take s places whenever the mscan12 arbitrates for the bus. this is also the case after the occurrence of a transmission error. when a high priority mess age is scheduled by the application software it may become necessary to abort a lower priority me ssage being set up in one of the three transmit buffers. as messages that are already under transmission cannot be abor ted, the user has to request the abort by setting the correspon ding abort request flag (abtrq) in the transmission control register (ctc r). the mscan12 grants the request, if possible, by setting the co rresponding abort request acknowledge (abtak) and the txe flag in order to release the buffer and by generating a transmit interr upt. the transmit inte rrupt handler software can tell from the sett ing of the abtak flag w hether the message was aborted (abtak=1) or sent in the meantim e (abtak=0). 17.5 identifier acceptance filter the identifier acceptance register s (cidar0?7) defi ne the acceptable patterns of the standard or exten ded identifier (id10?id0 or id28?id0). any of these bits can be marked don? t care in the identifier mask registers (cidmr0?7). a filter hit is indicated to the application software by a set rxf (receive buffer full flag, see mscan12 receiver fl ag register (crflg) ) and three bits in the identifier a cceptance control register (see mscan12 identifier acceptance control register (cidac) ). these identifier hit flags (idhit2?0) clearly i dentify the filter sect ion that caused the acceptance. they simplify the application software ?s task to identify the
mscan controller identifier acceptance filter mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor mscan controller 311 cause of the receiver interrupt. w hen more than one hi t occurs (two or more filters match) the lower hit has priority. a very flexible programmable generic identifier acceptance filter has been introduced in order to reduce the cpu interrupt loading. the filter is programmable to operate in four different modes: two identifier acceptanc e filters, each to be appl ied to a) the full 29 bits of the extended identifier and to the following bits of the can frame: rtr, ide, srr or b) the 11 bits of the standard identifier, the rtr an d ide bits of can 2. 0a/b messages. this mode implements two fi lters for a full lengt h can 2.0b compliant extended identifier. figure 17-3 shows how the firs t 32-bit filter bank (cidar0?3, cidmr0?3) produces a filter 0 hit. similarly, the second filter bank (cidar4?7, ci dmr4?7) produces a filter 1 hit. four identifier acceptance filters, each to be applied to a) the 14 most significant bits of the ex tended identifier pl us the srr and ide bits of can 2.0b messages or b) the 11 bits of the standard identifier, the rtr and ide bits of ca n 2.0a/b mesages. figure 17-4 shows how the first 32-bit f ilter bank (cidar0?3, cidmr0?3) produces filter 0 and 1 hits. similarly, the second filter bank (cidar4?7, cidmr4?7) produc es filter 2 and 3 hits. eight identifier acceptance filters, each to be applied to the first 8 bits of the identifier. this mode implements eight independent filters for the first 8 bits of a can 2.0a /b compliant standard identifier or of a can 2.0b compliant extended identifier. figure 17-5 shows how the first 32-bit f ilter bank (cidar0?3, cidmr0?3) produces filter 0 to 3 hits. sim ilarly, the second filter bank (cidar4?7, cidmr4?7) produc es filter 4 to 7 hits. closed filter. no can message will be copied into the foreground buffer rxfg, and the rxf fl ag will never be set.
mscan controller technical data mc68hc9 12d60a ? rev. 3.1 312 mscan controller freescale semiconductor figure 17-3. 32-bit maskable identifier acceptance filters figure 17-4. 16-bit m askable acceptance filters cidmr2 id28 id21 id20 id15 id14 id7 id6 rtr id10 id3 id2 ide ac7 idr0 idr0 idr1 idr1 idr2 idr3 ac0 ac7 ac0 ac7 ac7 ac0 ac0 ac7 ac0 ac7 ac0 ac7 ac0 ac7 ac0 cidmro cidmr1 cidmr3 cidar3 cidar2 cidar1 cidaro id accepted (filter 0 hit) id28 id21 id20 id15 id14 id7 id6 rtr id10 id3 id2 ide ac7 idr0 idr0 idr1 idr1 idr2 idr3 ac0 ac7 ac0 ac7 ac0 ac7 ac0 cidmro cidmr1 cidar1 cidaro id accepted (filter 0 hit) id accepted (filter 1 hit) ac7 ac0 ac7 ac0 ac7 ac0 ac7 ac0 cidmr2 cidmr3 cidar3 cidar2
mscan controller identifier acceptance filter mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor mscan controller 313 figure 17-5. 8-bit m askable acceptance filters id28 id21 id20 id15 id14 id7 id6 rtr id10 id3 id2 ide ac7 idr0 idr0 idr1 idr1 idr2 idr3 ac0 ac7 ac0 cidmro cidaro id accepted (filter 0 hit) ac7 ac0 ac7 ac0 cidmr1 cidar1 ac7 ac0 ac7 ac0 cidmr2 cidar2 id accepted (filter 1 hit) id accepted (filter 2 hit) ac7 ac0 ac7 ac0 cidmr3 cidar3
mscan controller technical data mc68hc9 12d60a ? rev. 3.1 314 mscan controller freescale semiconductor 17.6 interrupts the mscan12 supports four inte rrupt vectors mapped onto eleven different interrupt sources, any of which can be individually masked (for details see mscan12 receiver fl ag register (crflg) to mscan12 transmitter contro l register (ctcr) ): transmit interrupt : at least one of the th ree transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. the txe flags of the empty message buffers are set. receive interrupt : a message has been successfully received and loaded into the for eground receive buffer. this interrupt is generated immediately after rece iving the eof symbol. the rxf flag is set. wake-up interrupt : an activity on the can bus occurred during mscan12 internal sleep mode. error interrupt : an overrun, error or warning condition occurred. the receiver flag regi ster (crflg) indicate s one of the following conditions: ? overrun: an overrun conditi on as described in receive structures has occurred. ? receiver warning : the receive error counter has reached the cpu warning limit of 96. ? transmitter warning : the transmit error counter has reached the cpu warning limit of 96. ? receiver error passive : the receive error counter has exceeded the error passive limit of 127 and mscan12 has gone to error passive state. ? transmitter error passive : the transmit error counter has exceeded the error passive limit of 127 and mscan12 has gone to error passive state. ? bus off : the transmit error count er has exceeded 255 and mscan12 has gone to busoff state.
mscan controller interrupts mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor mscan controller 315 17.6.1 interrupt acknowledge interrupts are directly associated with one or more status flags in either the mscan12 receiver flag regist er (crflg) or the mscan12 transmitter flag register (ctflg). interrupts are pending as long as one of the corresponding flags is set. the flags in above registers must be reset within the interrupt handler in order to handshake the interrupt. the flags are reset through writing a 1 to the corresponding bit position. a flag cannot be cleared if the respecti ve condition st ill prevails. note: bit manipulation instructio ns (bset) shall not be used to clear interrupt flags. 17.6.2 interrupt vectors the mscan12 supports four inte rrupt vectors as shown in table 17-1 . the vector addresses and t he relative interrupt pr iority are dependent on the chip integrati on and to be defined. table 17-1. mscan12 interrupt vectors function source local mask global mask wake-up wupif wupie i bit error interrupts rwrnif rwrnie twrnif twrnie rerrif rerrie terrif terrie boffif boffie ovrif ovrie receive rxf rxfie tr a n s m i t txe0 txeie0 txe1 txeie1 txe2 txeie2
mscan controller technical data mc68hc9 12d60a ? rev. 3.1 316 mscan controller freescale semiconductor 17.7 protocol violation protection the mscan12 will protect the user from accident ally violating the can protocol through programming errors . the protection logic implements the following features: the receive and transmit error counters cannot be written or otherwise manipulated. all registers which control t he configuration of the mscan12 cannot be modified whil e the mscan12 is on-line. the sftres bit in cmcr0 (see mscan12 module cont rol register 0 (cmcr0) ) serves as a lock to prot ect the following registers: ? mscan12 module control register 1 (cmcr1) ? mscan12 bus timing register 0 and 1 (cbtr0, cbtr1) ? mscan12 identifier acceptance control register (cidac) ? mscan12 identifier accept ance registers (cidar0?7) ? mscan12 identifier mask registers (cidmr0?7) the txcan pin is forced to rece ssive when the mscan12 is in any of the low power modes. 17.8 low power modes in addition to normal mode, t he mscan12 has three modes with reduced power consumption: sleep, soft_reset and power_down mode. in sleep and soft_reset modes, power consumption is reduced by stopping all clocks except those to access the registers. in power_down mode, all clocks are stopped and no power is consumed. the wai and stop instructions put t he mcu in low power consumption stand-by modes. table 17-2 summarizes the comb inations of mscan12 and cpu modes. a particular combinat ion of modes is entered for the given settings of the bits cswai, slpak, and s ftres. for all modes, an mscan wake-up interrupt can occu r only if slpak=wupie=1. while the cpu is in wait mode, the mscan12 can be operated in normal
mscan controller low power modes mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor mscan controller 317 mode and generate inte rrupts (registers can be accessed via background debug mode). 17.8.1 mscan12 sleep mode the cpu can request the ms can12 to enter this low-power mode by asserting the slprq bi t in the module confi guration register (see figure 17-6 ). the time when the mscan 12 enters sleep mode depends on its activity: if there are one or more me ssage buffers are scheduled for transmission (txex = 0), the mscan will continue to transmit until all transmit message buffers ar e empty (txex = 1, transmitted successfully or aborted) and then goes into sleep mode. if it is receiving, it continues to receive a nd goes into sleep mode as soon as the can bus next becomes idle. if it is neither transmi tting nor receiving, it immediately goes into sleep mode. note: the application software must avoi d setting up a transmission (by clearing one or more txe flag(s)) and immediately request sleep mode (by setting slprq). it then depends on the exact sequence of table 17-2. mscan12 vs . cpu oper ating modes mscan mode cpu mode stop wait run power_down cswai = x (1) slpak = x sftres = x 1. x means don?t care. cswai = 1 slpak = x sftres = x sleep cswai = 0 slpak = 1 sftres = 0 cswai = x slpak = 1 sftres = 0 soft_reset cswai = 0 slpak = 0 sftres = 1 cswai = x slpak = 0 sftres = 1 normal cswai = 0 slpak = 0 sftres = 0 cswai = x slpak = 0 sftres = 0
mscan controller technical data mc68hc9 12d60a ? rev. 3.1 318 mscan controller freescale semiconductor operations whether the mscan12 star ts transmitting or goes into sleep mode directly. during sleep mode, the slpak flag is set. the application software should use slpak as a handshake in dication for the request (slprq) to go into sleep mode. when in sleep mode, the mscan12 stops its internal clocks. however, clocks to allow register ac cesses still run. if the mscan12 is in bus-off state, it stops counting the 128*11 consecutive recessive bits due to the stopped clocks. the txcan pin stays in recessive state. if rxf=1, th e message can be read and rxf can be cleared. copying of rxbg into rxfg doesn?t take place while in sleep mode. it is possible to access the transmit buffers and to clear the txe flags. no message abort takes place while in sleep mode. the mscan12 leaves sleep mode (wake-up) when bus activity occurs or the mcu clears the slprq bit or the mcu sets sftres. note: the mcu cannot clear the slprq bit before the mscan12 is in sleep mode (slpak = 1). after wake-up, the mscan12 waits fo r 11 consecutive recessive bits to synchronize to the bus. as a consequen ce, if the mscan 12 is woken-up by a can frame, this fr ame is not received. the receive message buffers (rxfg and rxbg) contain messages if they were received before sleep mode was entered. a ll pending actions are executed upon wake-up: copying of rxbg into rx fg, message aborts and message transmissions. if the mscan12 is st ill in bus-off st ate after sleep mode was left, it continues counting t he 128*11 consecutive recessive bits.
mscan controller low power modes mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor mscan controller 319 figure 17-6. sleep req uest / acknowledge cycle 17.8.2 mscan12 soft_reset mode in soft_reset mode, the mscan12 is stopped. registers can still be accessed. this mode is used to init ialize the module c onfiguration, bit timing, and t he can message filter. see mscan12 module control register 0 (cmcr0) for a complete descrip tion of the soft_reset mode. when setting the sftres bit, th e mscan12 immediately stops all ongoing transmissions and receptions, potentially c ausing the can protocol violations. note: the user is responsible for ensuri ng that the mscan12 is not active when soft_reset mode is enter ed. the recommended procedure is to bring the mscan12 in to sleep mode before t he sftres bit is set. mscan12 sleeping slprq = 1 slpak = 1 mscan12 running slprq = 0 slpak = 0 sleep request slprq = 1 slpak = 0 mcu mscan12 mcu or mscan12
mscan controller technical data mc68hc9 12d60a ? rev. 3.1 320 mscan controller freescale semiconductor 17.8.3 mscan12 power_down mode the mscan12 is in po wer_down mode when the cpu is in stop mode or the cpu is in wait mode and the cswai bit is set (see mscan12 module control register 0 (cmcr0) ). when entering the power_down mode, the mscan12 immediately stops all ongoing transmissions and re ceptions, potentially causing can protocol violations. note: the user is responsible for ensuri ng that the mscan12 is not active when power_down mode is entered. the re commended procedure is to bring the mscan12 into sle ep mode before the stop instruction (or the wai instruction, if cswai is set) is executed. to protect the can bus system from fa tal consequences of violations to the above rule, the mscan 12 drives the txcan pin into recessive state. in power_down mode no registers can be accessed. 17.8.4 programmable wake-up function the mscan12 can be progra mmed to apply a low-pa ss filter function to the rxcan input li ne while in sleep mode (see control bit wupm in the module control register, mscan12 module cont rol register 1 (cmcr1). ). this feature can be used to protect the mscan12 from wake-up due to short glit ches on the can bus li nes. such glitches can result from electrom agnetic interference wi thin noisy environments. 17.9 timer link the mscan12 generates a timer sig nal whenever a valid frame has been received. because the can spec ification defines a frame to be valid if no errors occurred before the eof field has been transmitted successfully, the timer signal is generat ed right after the eof. a pulse of one bit time is generated. as th e mscan12 receiver engine also
mscan controller clock system mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor mscan controller 321 receives the frames bei ng sent by itself, a time r signal is also generated after a successful transmission. the previously described timer sig nal can be routed into the on-chip timer interface module (ect). this signal is connected to the timer n channel m input (1) under the control of the ti mer link enable (tlnken) bit in the cmcr0. after timer n has been programmed to capture rising edge events, it can be used under software cont rol to generate 16-bit time stamps which can be stored with the received message. 17.10 clock system figure 17-7 shows the structure of t he mscan12 clo ck generation circuitry. with this flexible cl ocking scheme the mscan12 is able to handle can bus rates ra nging from 10 kb ps up to 1 mbps. figure 17-7. clocking scheme the clock source bit (clksrc) in the mscan12 module control register (cmcr1) (see mscan12 bus timing register 0 (cbtr0) ) defines whether the mscan12 is c onnected to the output of the crystal oscillator (extali) or to a clock twice as fast as the system clock (eclk). the clock source has to be chosen such that the ti ght oscillator tolerance requirements (up to 0.4%) of the can protocol ar e met. additionally, for high can bus rates (1 mbps), a 50% duty cycle of the clock is required. 1. the timer channel being used for the timer link is integration dependent. mscan12 cgm sysclk extali cgmcanclk prescaler (1...64) time quanta clock clksrc clksrc
mscan controller technical data mc68hc9 12d60a ? rev. 3.1 322 mscan controller freescale semiconductor note: if the system clock is generated from a pll, it is recommended to select the crystal clock source rather than the system clock source due to jitter considerations, especially at faster can bus rates. for microcontrollers without the cgm module, cgmcanclk is driven from the crystal o scillator (extali). a programmable prescaler is used to generate out of mscanclk the time quanta (tq) clock. a time quantum is the atom ic unit of time handled by the mscan12. a bit time is subdivi ded into three segments (1) : sync_seg: this segment has a fixed length of one time quantum. signal edges are expected to happen within this section. time segment 1: this segmen t includes the prop_seg and the phase_seg1 of the c an standard. it can be programmed by setting the parameter tseg1 to consist of 4 to 16 time quanta. time segment 2: this segment represents t he phase_seg2 of the can standard. it can be programmed by setting the tseg2 parameter to be 2 to 8 time quanta long. the synchronisation jump width can be programmed in a range of 1 to 4 time quanta by setti ng the sjw parameter. above parameters can be set by progr amming the bus ti ming registers (cbtr0?1, see mscan12 bus timing r egister 0 (cbtr0) and mscan12 bus timing r egister 1 (cbtr1). ). note: it is the user?s responsibil ity to make sure that his bit time settings are in compliance with the can standard. table 17-3 gives an overview on the can conforming segment settings and the rela ted parameter values. 1. for further explanation of the under-lying co ncepts please refer to is o/dis 11519-1, section 10.3. f t q f cgmcanclk presc value ? ------------------------------------------ - = bitrate f t q number of timequanta ?? ------------------------------------------------------------------------ =
mscan controller clock system mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor mscan controller 323 figure 17-8. segments within the bit time table 17-3. can standard compli ant bit time segment settings time segment 1 tseg1 time segment 2 tseg2 synchron. jump width sjw 5 .. 10 4 .. 9 2 1 1 .. 2 0 .. 1 4 .. 11 3 .. 10 3 2 1 .. 3 0 .. 2 5 .. 12 4 .. 11 4 3 1 .. 4 0 .. 3 6 .. 13 5 .. 12 5 4 1 .. 4 0 .. 3 7 .. 14 6 .. 13 6 5 1 .. 4 0 .. 3 8 .. 15 7 .. 14 7 6 1 .. 4 0 .. 3 9 .. 16 8 .. 15 8 7 1 .. 4 0 .. 3 sync _seg time segment 1 time seg. 2 1 4 ... 16 2 ... 8 8... 25 time quanta = 1 bit time nrz signal sample point (single or triple sampling) (prop_seg + phase_seg1) (phase_seg2) transmit point
mscan controller technical data mc68hc9 12d60a ? rev. 3.1 324 mscan controller freescale semiconductor 17.11 memory map the mscan12 occupies 128 bytes in the cpu12 memory space. the background receive buffer can on ly be read in test mode. figure 17-9. mscan12 memory map $0100 control registers 9 bytes $0108 $0109 reserved 5 bytes $010d $010e error counters 2 bytes $010f $0110 identifier filter 16 bytes $011f $0120 reserved 29 bytes $013c $013d port can registers 3 bytes $013f $0140 receive buffer $014f $0150 transmit buffer 0 $015f $0160 transmit buffer 1 $016f $0170 transmit buffer 2 $017f
mscan controller programmer?s model of message storage mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor mscan controller 325 17.12 programmer?s model of message storage the following section deta ils the organisation of the receive and transmit message buffers and the associated control registers. for reasons of programmer interface simplificati on the receive and transmit message buffers have the same outline. each message buf fer allocates 16 bytes in the memory map containing a 13 by te data structure. an additional transmit buffer priority register (tbpr ) is defined for t he transmit buffers. 17.12.1 message buffer outline figure 17-11 shows the common 13 byte da ta structure of receive and transmit buffers for ex tended identifiers. th e mapping of standard identifiers into the idr registers is shown in figure 17-12 . all bits of the 13 byte data structure ar e undefined out of reset. figure 17-10. message buffer organization address (1) 1. x is 4, 5, 6, or 7 depending on which buffer rxfg, tx0, tx1, or tx2 respectively. register name 01x0 identifier register 0 01x1 identifier register 1 01x2 identifier register 2 01x3 identifier register 3 01x4 data segment register 0 01x5 data segment register 1 01x6 data segment register 2 01x7 data segment register 3 01x8 data segment register 4 01x9 data segment register 5 01xa data segment register 6 01xb data segment register 7 01xc data length register 01xd transmit buffer priority register (2) 2. not applicable for receive buffers 01xe unused 01xf unused
mscan controller technical data mc68hc9 12d60a ? rev. 3.1 326 mscan controller freescale semiconductor note: the foreground receive buffer can be read anyti me but cannot be written. the transmit buffers can be r ead or written anytime. addr (1) register r/w bit 7 6 5 4 3 2 1 bit 0 $01x0 idr0 r id28 id27 id26 id25 id24 id23 id22 id21 w $01x1 idr1 r id20 id19 id18 srr (1) ide (1) id17 id16 id15 w $01x2 idr2 r id14 id13 id12 id11 id10 id9 id8 id7 w $01x3 idr3 r id6 id5 id4 id3 id2 id1 id0 rtr w $01x4 dsr0 r db7 db6 db5 db4 db3 db2 db1 db0 w $01x5 dsr1 r db7 db6 db5 db4 db3 db2 db1 db0 w $01x6 dsr2 r db7 db6 db5 db4 db3 db2 db1 db0 w $01x7 dsr3 r db7 db6 db5 db4 db3 db2 db1 db0 w $01x8 dsr4 r db7 db6 db5 db4 db3 db2 db1 db0 w $01x9 dsr5 r db7 db6 db5 db4 db3 db2 db1 db0 w $01xa dsr6 r db7 db6 db5 db4 db3 db2 db1 db0 w $01xb dsr7 r db7 db6 db5 db4 db3 db2 db1 db0 w $01xc dlr r dlc3 dlc2 dlc1 dlc0 w figure 17-11 1. x is 4, 5, 6, or 7 depending on which bu ffer rxfg, tx0, tx1, or tx2 respectively.
mscan controller programmer?s model of message storage mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor mscan controller 327 17.12.2 identifier registers (idrn) the identifiers consist of either 11 bits (id10?id0) for the standard, or 29 bits (id28?id0) for the extended format. id10/28 is the most significant bit and is transmitted firs t on the bus during the arbitration procedure. the priority of an identifier is defined to be highest for the smallest binary number. srr ? substitute remote request this fixed recessive bit is used only in extended format. it must be set to 1 by the user for transmission bu ffers and will be st ored as received on the can bus for receive buffers. ide ? id extended this flag indicates whet her the extended or standa rd identifier format is applied in this buffer. in the case of a receiv e buffer the flag is set as being received and i ndicates to the cpu how to process the buffer identifier registers. in the case of a transmit buf fer the flag indicates to the mscan12 what type of identifier to send. 0 = standard format (11-bit) 1 = extended format (29-bit) addr (1) registerr/wbit 7654321bit 0 $01x0 idr0 r id10 id9 id8 id7 id6 id5 id4 id3 w $01x1 idr1 r id2 id1 id0 rtr ide(0) w $01x2 idr2 r w $01x3 idr3 r w figure 17-12 1. x is 4, 5, 6, or 7 depending on which bu ffer rxfg, tx0, tx1, or tx2 respectively.
mscan controller technical data mc68hc9 12d60a ? rev. 3.1 328 mscan controller freescale semiconductor rtr ? remote tran smission request this flag reflects the st atus of the remote transmission request bit in the can frame. in the case of a receive buffer it indicates the status of the received frame and supports the transmission of an answering frame in software. in the case of a transmit buffer this flag defines the setting of the rtr bit to be sent. 0 = data frame 1 = remote frame 17.12.3 data length register (dlr) this register keeps t he data length field of the can frame. dlc3 ? dlc0 ? data length code bits the data length code contai ns the number of bytes (data byte count) of the respective message. at the tr ansmission of a remote frame, the data length code is transmitted as programm ed while the number of transmitted data bytes is always 0. the data by te count ranges from 0 to 8 for a data frame. table 17-4 shows the effect of setting the dlc bits. table 17-4. data length codes data length code data byte count dlc3 dlc2 dlc1 dlc0 00000 00011 00102 00113 01004 01015 01106 01117 10008
mscan controller programmer?s model of message storage mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor mscan controller 329 17.12.4 data segment registers (dsrn) the eight data segment registers cont ain the data to be transmitted or being received. the number of bytes to be transmitted or being received is determined by the data leng th code in the corresponding dlr. 17.12.5 transmit buffer pr iority registers (tbpr) prio7 ? prio0 ? local priority this field defines the lo cal priority of the associated message buffer. the local priority is used for the inte rnal prioritisation process of the mscan12 and is defined to be highest fo r the smallest binary number. the mscan12 implements the follo wing internal prioritisation mechanism: all transmission buffers with a cl eared txe flag par ticipate in the prioritisation immediately before the sof (start of fr ame) is sent. the transmission buffer with the lowe st local priority field wins the prioritisation. in cases of more than one buffer having the same lowest priority, the message buffer with the lower index number wins. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tbpr (1) 1. x is 5, 6, or 7 depending on which buf fer tx0, tx1, or tx2 respectively. r prio7 prio6 prio5 prio4 prio3 prio2 prio1 prio0 $01xd w reset ? ? ? ?????
mscan controller technical data mc68hc9 12d60a ? rev. 3.1 330 mscan controller freescale semiconductor 17.13 programmer?s mode l of control registers 17.13.1 overview the programmer?s model ha s been laid out for maximum simplicity and efficiency. 17.13.2 mscan12 module cont rol register 0 (cmcr0) cswai ? can stops in wait mode 0 = the module is not affe cted during wait mode. 1 = the module ceases to be clocked during wait mode. synch ? synchronized status this bit indicates whet her the mscan12 is synchronized to the can bus and as such can participate in the co mmunication process. 0 = mscan12 is not sync hronized to the can bus 1 = mscan12 is synchr onized to the can bus tlnken ? timer enable this flag is used to establish a link between the mscan12 and the on- chip timer (see timer link ). 0 = the port is connected to the timer input. 1 = the mscan12 timer signal out put is connected to the timer input. bit 7654321bit 0 cmcr0 r 0 0 cswai synch tlnken slpak slprq sftres $0100 w reset00100001
mscan controller programmer?s model of control registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor mscan controller 331 slpak ? sleep m ode acknowledge this flag indicates whether the ms can12 is in module internal sleep mode. it shall be used as a handshak e for the sleep mode request (see mscan12 sleep mode ). 0 = wake-up ? the mscan12 is not in sleep mode. 1 = sleep ? the mscan12 is in sleep mode. slprq ? sleep request this flag allows to reques t the mscan12 to go into an internal power- saving mode (see mscan12 sleep mode ). 0 = wake-up ? the mscan12 will function normally. 1 = sleep request ? the mscan12 will go into sleep mode when the can bus is idle, i.e. the module is not receiving a message and all transmi t buffers are empty. sftres? soft_reset when this bit is set by the cpu, the mscan12 immedi ately enters the soft_reset state. any ongoing transmission or reception is aborted and synchronisation to the bus is lost. the following registers will go into and stay in the same state as out of hard reset: cmcr0, crflg, crier, ctflg, ctcr. the registers cmcr1, cbtr0, cb tr1, cidac, cidar0?3, cidmr0?3 can only be written by the cpu when the mscan12 is in soft_reset state. the values of the error counters are not affected by soft_reset. when this bit is cleared by the cpu, the mscan 12 will try to synchronize to the can bus: if t he mscan12 is not in busoff state it will be synchroniz ed after 11 recessive bits on the bus; if the mscan12 is in busoff state it cont inues to wait for 128 occurrences of 11 recessive bits. clearing sftres and writi ng to other bits in cmcr0 must be in separate instructions. 0 = normal operation 1 = mscan12 in soft_reset state.
mscan controller technical data mc68hc9 12d60a ? rev. 3.1 332 mscan controller freescale semiconductor 17.13.3 mscan12 module cont rol register 1 (cmcr1). loopb ? loop back self test mode when this bit is set the mscan 12 performs an internal loop back which can be used for self test opera tion: the bit stream output of the transmitter is fed back to the rece iver internally. the rxcan input pin is ignored and the txcan output goes to the re cessive state (1). the mscan12 behaves as it does norma lly when transmitt ing and treats its own transmitted messa ge as a message receiv ed from a remote node. in this state the mscan12 ig nores the bit sent during the ack slot of the can frame a cknowledge field to insu re proper re ception of its own message. both transmit and receive interrupts are generated. 0 = normal operation 1 = activate loop back self test mode wupm ? wake-up mode this flag defines whether the integr ated low-pass filter is applied to protect the mscan12 from spurious wake-ups (see programmable wake-up function ). 0 = mscan12 will wake up t he cpu after any recessive to dominant edge on the can bus. 1 = mscan12 will wake up the cpu on ly in the case of dominant pulse on the bus which has a length of at least approximately t wup . clksrc ? mscan 12 clock source this flag defines which clock source the mscan12 module is driven from (only for system with cgm module; see clock system , figure 17-7 ). 0 = the mscan12 clock source is extali. 1 = the mscan12 clock source is sysclk, twice the frequency of eclk. note: the cmcr1 register can be written only if the sft res bit in cmcr0 is set. bit 7654321bit 0 cmcr1r00000 loopb wupm clksrc $0101 w reset 0 0 000000
mscan controller programmer?s model of control registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor mscan controller 333 17.13.4 mscan12 bus timi ng register 0 (cbtr0) sjw1, sjw0 ? synchronization jump width the synchronization jump width defi nes the maximum number of time quanta (tq) clock cycles by whic h a bit may be shortened, or lengthened, to achieve resynchron ization on data transitions on the bus (see table 17-5 ). brp5 ? brp0 ? b aud rate prescaler these bits determine the time quanta ( tq) clock, which is used to build up the individual bi t timing, according to table 17-6 . note: the cbtr0 register can only be writte n if the sftres bit in cmcr0 is set. bit 7654321bit 0 cbtr0 r sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 $0102 w reset 00000000 table 17-5. synchronization jump width sjw1 sjw0 synchronization jump width 0 0 1 tq clock cycle 0 1 2 tq clock cycles 1 0 3 tq clock cycles 1 1 4 tq clock cycles table 17-6. baud rate prescaler brp5 brp4 brp3 brp2 brp1 brp0 prescaler value (p) 000000 1 000001 2 000010 3 000011 4 :::::: : :::::: : 111111 64
mscan controller technical data mc68hc9 12d60a ? rev. 3.1 334 mscan controller freescale semiconductor 17.13.5 mscan12 bus timi ng register 1 (cbtr1). samp ? sampling this bit determines the number of samples of the serial bus to be taken per bit time. if se t three samples per bit are taken, the regular one (sample point) and two preceding sa mples, using a majority rule. for higher bit rates samp should be cleared, which means that only one sample will be taken per bit. 0 = one sample per bit. 1 = three samples per bit. (1) tseg22 ? tseg10 ? time segment time segments within the bit time fix the number of clock cycles per bit time, and the location of the sample point. (see figure 17-8 ) time segment 1 (tseg1) and time segment 2 (tseg2) are programmable as shown in table 17-8 . bit 7654321bit 0 cbtr1 r samp tseg22 tseg21 tseg20 t seg13 tseg12 tseg11 tseg10 $0103 w reset 00000000 1. in this case, phase_seg1 must be at least two time quanta. table 17-7. time segment syntax sync_seg system expects transitions to occur on the bus during this period. transmit point a node in transmit mode will transfer a new value to the can bus at this point. sample point a node in receive mode will sample the bus at this point. if the three samples per bit option is selected then this point marks the position of the third sample.
mscan controller programmer?s model of control registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor mscan controller 335 the bit time is determined by the oscillator frequen cy, the baud rate prescaler, and the number of time quanta (tq) clock cycles per bit (as shown above). note: the cbtr1 register can only be written if the sftres bit in cmcr0 is set 17.13.6 mscan12 receiver flag register (crflg) all bits of this register are read and clear only. a flag can be cleared by writing a 1 to the corresponding bit position. a flag can only be cleared when the condition which caused the setting is no more valid. writing a 0 has no effect on the flag setting. every flag has an associated interrupt enable flag in the crier register. a hard or soft reset clears the register. wupif ? wake-up interrupt flag if the mscan12 detects bus activity while in sleep mode, it sets the wupif flag. if not masked, a wake -up interrupt is pending while this flag is set. 0 = no wake-up activity has bee n observed while in sleep mode. 1 = mscan12 has det ected activity on the bus and requested wake-up. table 17-8. time segment values tseg13 tseg12 tseg11 tseg10 time segment 1 tseg22 tseg21 tseg20 time segment 2 0 0 0 0 1 tq clock cycle 0 0 0 1 tq clock cycle 0 0 0 1 2 tq clock cycles 0 0 1 2 tq clock cycles 0 0 1 0 3 tq clock cycles . . . . 0 0 1 1 4 tq clock cycles . . . . . . . . . 1 1 1 8 tq clock cycles .... . 1 1 1 1 16 tq clock cycles bittime presc value ? f cgmcanclk ------------------------------------------ - number ? of timequanta tt = bit 7654321bit 0 crflg r wupif rwrnif twrnif rerri f terrif boffif ovrif rxf $0104 w reset 0 0 000000
mscan controller technical data mc68hc9 12d60a ? rev. 3.1 336 mscan controller freescale semiconductor rwrnif ? receiver wa rning interrupt flag this flag is set when the mscan12 goes into warning status due to the receive error counter (rec) e xceeding 96 and nei ther one of the error interrupt flags or the bus-off interrupt flag is set (1) . if not masked, an error interrupt is pen ding while this flag is set. 0 = no receiver warning status has been reached. 1 = mscan12 went into receiver warning status. twrnif ? transmitter wa rning interrupt flag this bit will be set w hen the mscan12 goes in to warning status due to the transmit error counter (tec) exceeding 96 and neither one of the error interrupt flags or the bus-off interrupt flag is set (2) . if not masked, an error interrupt is pen ding while this flag is set. 0 = no transmitter warning status has been reached. 1 = mscan12 went into transmitter warning status. rerrif ? receiver error passive interrupt flag this flag is set when the mscan12 goes into error passive status due to the receive error counter (rec) exceeding 127 and the bus-off interrupt flag is not set (3) . if not masked, an error interrupt is pending while this flag is set. 0 = no receiver error pa ssive status has been reached. 1 = mscan12 went in to receiver erro r passive status. terrif ? transmitter error passive interrupt flag this flag is set when the mscan12 goes into error passive status due to the transmit error counter (tec) exceeding 127 and the bus-off interrupt flag is not set (4) . if not masked, an error interrupt is pending while this flag is set. 0 = no transmitter error passi ve status has been reached. 1 = mscan12 went in to transmitter error passive status. 1. condition to set the flag: rwrnif = (96 rec 127) & rerrif & terrif & boffif 2. condition to set t he flag: twrnif = (96 tec 127) & rerrif & terrif & boffif 3. condition to set t he flag: rerrif = (128 rec 255) & boffif 4. condition to set the flag: terrif = (128 tec 255) & boffif
mscan controller programmer?s model of control registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor mscan controller 337 boffif ? busoff interrupt flag this flag is set when the mscan12 goes into busoff status, due to the transmit error count er exceeding 255. it c annot be cleared before the mscan12 has monitor ed 128 times 11 consecutive recessive bits on the bus. if not masked, an error in terrupt is pending while this flag is set. 0 = no busoff stat us has been reached. 1 = mscan12 went in to busoff status. ovrif ? overrun interrupt flag this flag is set w hen a data overrun condition occurrs. if not masked, an error interrupt is pending while this flag is set. 0 = no data overrun has occurred. 1 = a data overrun has been detected. rxf ? receive buffer full the rxf flag is set by the mscan12 when a new message is available in the foreground receive buffer. this flag indicates whether the buffer is loaded with a correct ly received message. after the cpu has read that message from the receiv e buffer, the rxf flag must be handshaken (cleared) in or der to release the buf fer. a set rxf flag prohibits the exchange of the background rece ive buffer into the foreground buffer. if not masked, a receive interrupt is pending while this flag is set. 0 = the receive buffer is released (not full). 1 = the receive buffer is full . a new message is available. warning: to ensure data integrity, no register s of the receive buffer shall be read while the rxf flag is cleared. note: the crflg register is held in the re set state when the sftres bit in cmcr0 is set.
mscan controller technical data mc68hc9 12d60a ? rev. 3.1 338 mscan controller freescale semiconductor 17.13.7 mscan12 receiver interrup t enable regi ster (crier) wupie ? wake-up interrupt enable 0 = no interrupt is generated from this event. 1 = a wake-up event result s in a wake-up interrupt. rwrnie ? receiver wa rning interrupt enable 0 = no interrupt is generated from this event. 1 = a receiver wa rning status event result s in an error interrupt. twrnie ? transmitter wa rning interrupt enable 0 = no interrupt is generated from this event. 1 = a transmitter warning status ev ent results in an error interrupt. rerrie ? receiver error passive interrupt enable 0 = no interrupt is generated from this event. 1 = a receiver error passive st atus event results in an error interrupt. terrie ? transmitter erro r passive interrupt enable 0 = no interrupt is generated from this event. 1 = a transmitter error passive st atus event resu lts in an error interrupt. boffie ? busoff interrupt enable 0 = no interrupt is generated from this event. 1 = a busoff event result s in an error interrupt. ovrie ? overrun interrupt enable 0 = no interrupt is generated from this event. 1 = an overrun event resu lts in an error interrupt. bit 7654321bit 0 crier r wupie rwrnie twrnie rerrie t errie boffie ovrie rxfie $0105 w reset 0 0 000000
mscan controller programmer?s model of control registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor mscan controller 339 rxfie ? receiver full interrupt enable 0 = no interrupt is generated from this event. 1 = a receive buffer fu ll (successful message reception) event results in a receive interrupt. note: the crier register is held in the rese t state when the sftres bit in cmcr0 is set. 17.13.8 mscan12 transmitte r flag register (ctflg) the abort acknowle dge flags are read only. the transmitter buffer empty flags are read and clear on ly. a flag can be clear ed by writing a 1 to the corresponding bit position. writing a zero has no effe ct on the flag setting. the transmitter buffer empty flags ea ch have an asso ciated interrupt enable bit in the ctcr regi ster. a hard or soft re set resets the register. abtak2 ? abtak0 ? abort acknowledge this flag acknowledges that a me ssage has been ab orted due to a pending abort request from the cpu. after a particular message buffer has been flagged empty, th is flag can be used by the application software to identif y whether the message has been aborted successfully or has been sent in the meantim e. the abtakx flag is cleared implicitly whenever the corresponding txe flag is cleared. 0 = the massage has no t been aborted, thus has been sent out. 1 = the message ha s been aborted. txe2 ? txe0 ?transmi tter buffer empty this flag indicates that the associat ed transmit message buffer is empty, thus not scheduled for transmission . the cpu must handshake (clear) the flag after a message has been set up in the transmit buffer and is due for transmission. the msc an12 sets the flag afte r the message has been sent successfully. the flag is al so set by the ms can12 when the bit 7654321bit 0 ctflg r 0 abtak2 abtak1 abtak0 0 txe2 txe1 txe0 $0106 w reset 0 0 0 0 0 1 1 1
mscan controller technical data mc68hc9 12d60a ? rev. 3.1 340 mscan controller freescale semiconductor transmission request was successfully aborted du e to a pending abort request ( mscan12 transmitter control register (ctcr) ). if not masked, a transmit interrupt is pending while this flag is set. clearing a txex flag al so clears the corresponding abtakx flag (see above). when a txex flag is set, the corresponding abtrqx bit is cleared (see mscan12 transmitter con trol register (ctcr) ). 0 = the associated message buffer is full (loaded wi th a message due for transmission). 1 = the associated message buffer is empty (not scheduled). warning: to ensure data integrity, no registers of the transmit buffers should be written to while the associat ed txe flag is cleared. note: the ctflg register is held in the reset stat e if the sftres bit cmcr0 is set. 17.13.9 mscan12 transmitter control register (ctcr) abtrq2 ? abtrq0 ? abort request the cpu sets an abtrqx bit to r equest that a scheduled message buffer (txex = 0) shall be aborted. the mscan12 grants the request if the message has not already started transm ission, or if the transmission is not successful (los t arbitration or error). when a message is aborted the associat ed txe and the abort acknowledge flag (abtak, see mscan12 transmitter fl ag register (ctflg) ) are set and an txe interrupt is generated if en abled. the cpu cannot reset abtrqx. abtrqx is clear ed implicitly whenever the associated txe flag is set. 0 = no abort request. 1 = abort request pending. note: the software must not clear one or mo re of the txe flags in ctfgl and simultaneously set the res pective abtrq bit(s). bit 7654321bit 0 ctcr r 0 abtrq2 abtrq1 abtrq0 0 txeie2 txeie1 txeie0 $0107 w reset 00000000
mscan controller programmer?s model of control registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor mscan controller 341 txeie2 ? txeie0 ? transmitt er empty interrupt enable 0 = no interrupt will be generated from this event. 1 = a transmitter empty (transmit buffer available for transmission) event will result in a tr ansmitter empty interrupt. note: the ctcr register is held in the reset state when t he sftres bit in cmcr0 is set. 17.13.10 mscan12 identi fier acceptance control register (cidac) idam1 ? idam0 ? identifier a cceptance mode the cpu sets these flags to define the i dentifier acceptance filter organisation (see identifier acceptance filter ). table 17-8 summarizes the different setti ngs. in filter closed mode no messages are accepted such that the for eground buffer is never reloaded. bit 7654321bit 0 cidac r 0 0 idam1 idam0 0 idhit2 idhit1 idhit0 $0108 w reset 0 0 0 0 0 0 0 0 table 17-9. identifier acceptance mode settings idam1 idam0 identif ier acceptance mode 0 0 two 32 bit acceptance filters 0 1 four 16 bit acceptance filters 1 0 eight 8 bit acceptance filters 1 1 filter closed
mscan controller technical data mc68hc9 12d60a ? rev. 3.1 342 mscan controller freescale semiconductor idhit2 ? idhit0 ? i dentifier acceptance hit indicator the mscan12 sets these flags to indi cate an identifier acceptance hit (see identifier acceptance filter ). table 17-8 summarizes the different settings. the idhit indicators ar e always related to the message in the foreground buffer. w hen a message gets copied from the background to the foreground buffer the indicators are updated as well. note: the cidac register can onl y be written if the s ftres bit in cmcr0 is set. 17.13.11 mscan12 receive error counter (crxerr) this register reflec ts the status of the msc an12 receive error counter. the register is read only. table 17-10. identifier ac ceptance hit indication idhit2 idhit1 idhit0 iden tifier acceptance hit 0 0 0 filter 0 hit 0 0 1 filter 1 hit 0 1 0 filter 2 hit 0 1 1 filter 3 hit 1 0 0 filter 4 hit 1 0 1 filter 5 hit 1 1 0 filter 6 hit 1 1 1 filter 7 hit bit 7654321bit 0 crxerr r rxerr7 rxerr6 rxerr5 rxer r4 rxerr3 rxerr2 rxerr1 rxerr0 $010e w reset 00000000
mscan controller programmer?s model of control registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor mscan controller 343 17.13.12 mscan12 transmit error counter (ctxerr) this register reflects t he status of the mscan12 transmit error counter. the register is read only. note: both error counters must only be read when in sleep or soft_reset mode. 17.13.13 mscan12 iden tifier acceptance registers (cidar0?7) on reception each message is writ ten into the ba ckground receive buffer. the cpu is only signalled to read the me ssage however, if it passes the criteria in the identi fier acceptance and identifier mask registers (accepted); ot herwise, the message is overwritten by the next message (dropped). the acceptance registers of the ms can12 are applied on the idr0 to idr3 registers of in coming messages in a bit by bit manner. for extended identifiers all four acceptance and mask registers are applied. for standard i dentifiers only the fi rst two (cidmr0/1 and cidar0/1) are applied. bit 7654321bit 0 ctxerr r txerr7 txerr6 txerr5 txer r4 txerr3 txerr2 txerr1 txerr0 $010f w reset 0 0 000000
mscan controller technical data mc68hc9 12d60a ? rev. 3.1 344 mscan controller freescale semiconductor ac7 ? ac0 ? acc eptance code bits ac7 ? ac0 comprise a user defined sequence of bits with which the corresponding bits of th e related identifier regi ster (idrn) of the receive message buffer are compared. the result of this comparison is then masked with the corres ponding identifier mask register. note: the cidar0?7 registers can only be wr itten if the sftres bit in cmcr0 is set. bit 7654321bit 0 cidar0 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 $0110 w cidar1 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 $0111 w cidar2 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 $0112 w cidar3 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 $0113 w reset???????? bit 7654321bit 0 cidar4 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 $0118 w cidar5 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 $0119 w cidar6 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 $011a w cidar7 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 $011b w reset????????
mscan controller programmer?s model of control registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor mscan controller 345 17.13.14 mscan12 i dentifier mask r egisters (cidmr0?7) the identifier mask register specifies which of the corres ponding bits in the identifier acceptance r egister are relevant for acceptance filtering. to receive standard identifiers in 32 bit fi lter mode it is required to program the last three bits (am2?am0) in the mask registers cidmr1 and cidmr5 to ?don?t care?. to receiv e standard identifiers in 16 bit filter mode it is required to pr ogram the last three bits (am2?am0) in the mask registers cidmr1, cidmr3, cidmr5 and cidmr7 to ?don?t care?. bit 7654321bit 0 cidmr0 r am7 am6 am5 am4 am3 am2 am1 am0 $0114 w cidmr1 r am7 am6 am5 am4 am3 am2 am1 am0 $0115 w cidmr2 r am7 am6 am5 am4 am3 am2 am1 am0 $0116 w cidmr3 r am7 am6 am5 am4 am3 am2 am1 am0 $0117 w reset???????? bit 7654321bit 0 cidmr4 r am7 am6 am5 am4 am3 am2 am1 am0 $011c w cidmr5 r am7 am6 am5 am4 am3 am2 am1 am0 $011d w cidmr6 r am7 am6 am5 am4 am3 am2 am1 am0 $011e w cidmr7 r am7 am6 am5 am4 am3 am2 am1 am0 $011f w reset????????
mscan controller technical data mc68hc9 12d60a ? rev. 3.1 346 mscan controller freescale semiconductor am7 ? am0 ? acceptance mask bits if a particular bit in th is register is cleared this indicates that the corresponding bit in the identifier acce ptance register must be the same as its identifier bit, before a matc h is detected. the messageis accepted if all such bits match. if a bit is se t, it indicates that the state of the corresponding bit in the identifier acceptance regi ster does not affect whether or not the message is accepted. bit description: 0 = match corresponding acceptanc e code register and identifier bits. 1 = ignore corresponding accept ance code r egister bit. note: the cidmr0?7 registers can only be wr itten if the sf tres bit in cmcr0 is set. 17.13.15 mscan12 port can c ontrol register (pctlcan) the following bits contro l pins 7 through 2 of po rt can. pins 1 and 0 are reserved for the rxcan (input only) and txcan (output only) pins. pupcan ? pull-up enable port can 0 = pull mode dis abled for port can. 1 = pull mode enabled for port can. in 80qfp all portcan[2: 7] pins should either be defined as outputs or have their pull-ups enabled. rdpcan ? reduced drive port can 0 = reduced drive dis abled for port can. 1 = reduced drive enabled for port can. bit 7654321bit 0 pctlcanr000000 pupcan rdpcan $013d w reset 0 0 0 0 0 0 0 0
mscan controller technical data mc68hc9 12d60a ? rev. 3.1 347 mscan controller freescale semiconductor 17.13.16 mscan12 port can da ta register (portcan) pcan7 ? pcan2 ? port can data bits (not available in 80qfp) writing to pcanx stores the bit va lue in an internal bit memory. this value is driven to the respec tive pin only if ddcanx = 1. reading pcanx returns the value of the internal bit memo ry driven to the pi n, if ddcanx = 1 the value of the respecti ve pin, if ddcanx = 0 reading bits 1 and 0 returns the va lue of the txcan and rxcan pins, respectively. 17.13.17 mscan12 port can data direction regi ster (ddrcan) ddrcan register determines the primary direction for the port can pins which are available as general pur pose i/o. the value in the ddrcan also affects the source of data fo r reads of the co rresponding port can register. when the ddc anx = 0 (input), the pi n is read. when the ddcanx =1 (output), the internal bit memory is read. ddcan7 ? ddcan2 ? data direction port can bits 0 = respective i/o pin is configured for input. 1 = respective i/o pin is configured for output. bit 7654321bit 0 portcan r pcan7 pcan6 pcan5 pcan4 pcan3 pcan2 txcan rxcan $013e w reset 0 0 0 0 0 0 0 0 bit 7654321bit 0 ddrcan r ddcan7 ddcan6 ddcan5 ddcan4 ddcan3 ddcan2 00 $013f w reset 0 0 0 0 0 0 0 0
mscan controller technical data mc68hc9 12d60a ? rev. 3.1 348 mscan controller freescale semiconductor
mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor analog-to-digital converter 349 technical data ? mc68hc912d60a section 18. analog-to-digital converter 18.1 contents 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 18.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 18.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352 18.5 atd operational modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 18.6 atd operation in different mcu modes . . . . . . . . . . . . . . . . 355 18.7 general purpose digital input port operation . . . . . . . . . . . . 357 18.8 application considerations . . . . . . . . . . . . . . . . . . . . . . . . . . .358 18.9 atd registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 18.2 introduction the 112tqfp version of the mc68hc9 12d60a has two identical atd modules identified as atd0 and atd1. except for the v dda and v ssa analog supply voltage, all pins are duplicated and i ndexed with ?0? or ?1? in the following description. an ?x? indicates either ?0? or ?1?. the 80qfp version has only one atd available, atd0. atd1 is not bonded out. as this module defaults to disabled on reset and it's i/o are inputs by default it r equires no configuration. the atd module is an 8-channel, 10-bit or 8-bit, multiplexed-input, successive-approximation analog-to-dig ital converter. it does not require external sample and hold circ uits because of the type of charge redistribution technique used. the atd converter timing can be synchronized to the system pclk. the atd module consists of a 16- word (32-byte) memory-mapped control register block used for control, testing and configuration.
analog-to-digital converter technical data mc68hc9 12d60a ? rev. 3.1 350 analog-to-digital converter freescale semiconductor 18.2.1 features ? 8/10 bit resolution ? 10 s, 10-bit single conversion time ? sample and transfer buffer amplifier ? programmable sample time ? left/right justified result data ? conversion completion interrupt ? analog input mult iplexer for 8 anal og input channels ? analog/digital inpu t pin multiplexing ? 1, 4, 8 conversion sequence lengths ? continuous conversion mode ? multiple channel scans figure 18-1. analog-to-digi tal converter block diagram mode and timing controls atd 0 atd 1 atd 2 atd 3 atd 4 atd 5 atd 6 atd 7 sar rc dac array and comparator internal bus v dda v ssa v rlx v rhx clock select/prescale analog mux and sample buffer amp port ad data input register anx7/padx7 anx6/padx6 anx5/padx5 anx4/padx4 anx3/padx3 anx2/padx2 anx1/padx1 anx0/padx0 reference supply hc12 atd block
analog-to-digital converter modes of operation mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor analog-to-digital converter 351 18.3 modes of operation analog to digital conversions are pe rformed in a variety of different programmable sequences referred to as conversion modes. each conversion mode is defined by: how many a/d conversions (one, f our or eight) are performed in a sequence which analog input channels ar e examined during a sequence the sample time length whether sequences are perform ed continuously or not result register assignments the modes are defined by the settings of three control bits (in atdctl5) mult controls whether the s equence examines a single analog input channel or scans a num ber of different channels scan determines if sequences are performed continuously sc determines if we are perfor ming a special conversion i.e. converting v rl , v rh , (v rl +v rh )/2 (usually used for test purposes). and three contro l values cc/cb/ca (in atdctl5) define the input channel(s) to be examined s8c/s1c (in atdctl3/5) define the number of conversions in a sequence smp0/smp1 (in atdctl4) define t he length of the sample time. sequences are initiated or halted by writing to control registers atdctl4 and atdctl5. for the continuous sequence modes, co nversions will not stop until another non-continuous conver sion sequence is initiated and finishes the atd is powered do wn (adpu control bit) the atd is reset
analog-to-digital converter technical data mc68hc9 12d60a ? rev. 3.1 352 analog-to-digital converter freescale semiconductor wait is executed (if the aswa i bit is activated) stop is executed. the mcu can discover when result dat a is available in the result registers with an interrupt on seq uence complete or by polling the conversion complete flags the scf bit is set after the co mpletion of each sequence. the ccf bit associated with each re sult register is set when that register is loaded with result data. note: atd conversion modes should not be confused with mcu operating modes such as stop, wait, idle, run, debug, and special (test) modes or with module defined operating modes such as power down, fast flag clear, 8-bit reso lution, 10-bit resolution, interrupt enable, clock prescaler setting, and freeze modes; and finally do not confuse with module result data formats such as right justify mode and left justify mode. 18.4 functional description 18.4.1 analog input multiplexer the analog input multiplexer selects one of the 8 exte rnal analog input channels to generate an analog sample. the input analog signals are unipolar and must fall within the potential r ange of vssa to vdda (analog electronics supply potentials). 18.4.2 sample bu ffer amplifier a sample amplifier is used to buffe r the input analog signal so that a storage node can be quickly char ged to the sample potential.
analog-to-digital converter functional description mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor analog-to-digital converter 353 18.4.3 sample and hold stage a sample and hold (s/h) stage accept s the analog signal from the input multiplexer and stores it as a capacitor char ge on a storage node in the module. the sample process uses a three stage approach: 1. the input signal is samp led onto a sample capacitor (for 2 module clocks). 2. the sample amplifier quickly c harges the storage node with a copy of the sample capacitor potential (for 4 module clocks). 3. the input signal is connected directly to the storage node to complete the sample for high accu racy (for 2, 4, 8 or 16 module clocks). longer sample times allo w accurate measurement of higher impedance sources. this charge redistribution method el iminates the need for external sample-and-hold circuitry. 18.4.4 analog-to-digit al converter submodule the analog-to-digital (a/d) machine uses a successive approximation a/d architecture to perform analog to digital conversi ons. the resolution of the a/d converter is se lectable at either 8 or 10 bits. it functions by comparing the stored analog sample potential wit h a series of digitally generated analog potentials (using cdac & rdac arra ys). by following a binary search algorithm, the converter quickly locates the approximating potential that is nearest to the sampled pot ential. at the end of the conversion pr ocess (10 module clocks for 8-bit, 12 module clocks for 10-bit), the successive approximation r egister (sar) contains the nearest appr oximation to the samp led signal, given the resolution of the a/d co nverter, and is transfe rred to the appropriate results register in the selected format. 18.4.5 clock prescaler function to keep the atd module clock with in the specified frequency range (note: there is a mini mum and maximum frequency), a clock prescaler function is available. this function divides the system pclk by a
analog-to-digital converter technical data mc68hc9 12d60a ? rev. 3.1 354 analog-to-digital converter freescale semiconductor programmable constant in order to generate the at d module?s internal clock. one additional benefit of the prescaled clo ck feature is that it allows the user further control ov er the sample per iod (note that changing the module clock also affects conversion time). the prescaler is based on a 5 bit modul us counter and divides the pclk by an integer value be tween 1 and 32. the final clock frequency is obtained with a further division by 2. the internal atd module clock and the system pclk have a direct phase relationship, however the at d module operates as if it is effectively asynchronous to mcu bus clock cycles. 18.5 atd operational modes 18.5.1 power down mode the atd module can be power ed down under program control. this is done by turning the clock signals off to the digital electronics of the module and eliminating th e quiescent current dr aw of the analog electronics. power down control is implem ented in one of three ways. 1. using the adpu bit in co ntrol register atdctl2. 2. when stop instruction is execut ed, the module will power down for the duration of the stop function. 3. if the module wait enable bi t (aswai) is set and a wait instruction is executed, the module will power down for the duration of the wait function. note that the reset default for the adp u bit is zero. therefore, when this module is reset, it is rese t into the power down state. once the command to power down has been re ceived, the atd module aborts any conversion sequence in progress and ente rs lower power mode. when the module is powered up again, the bi as settings in the analog electronics must be given time to stabilize before conversions
analog-to-digital converter atd operation in dif ferent mcu modes mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor analog-to-digital converter 355 can be performed. note that poweri ng up the module does not reset the module since the register file is not initialized. in power down mode, the control and result regi sters are still accessible. 18.5.2 idle mode idle mode for the atd module is def ined as the stat e where the atd module is powered up and ready to perform an a/d conversion, but not actually performing a conversion at the present time. access to all control, status, and re sult registers is available. the module is consuming near maximum power. note: when not active, the sample- and-hold and analog-to-digital sub- modules disable the clocks at their inputs to conserve power. the analog electronics still draw quiescent current. 18.5.3 run mode run mode for the atd m odule is defined as t he state where the atd module is powered up and currently performing an a/d conversion. complete assess to all con trol, status and result registers is available. the module is consum ing maximum power. 18.6 atd operation in different mcu modes 18.6.1 stop mode asserting stop causes the atd module to power down. the digital clocks are disabled and the analog quiescent current draw is turned off; this places the module into its power down state and is equivalent to clearing the adpu control bit in atdctl2.
analog-to-digital converter technical data mc68hc9 12d60a ? rev. 3.1 356 analog-to-digital converter freescale semiconductor 18.6.2 wait mode if the aswai control bi t in atdctl2 is set, then the atd responds to wait mode. if the aswai control bi t is clear, then th e atd ignores the wait signal. the atd response to the wa it mode is to power down the module. in this mode, the mcu does not have access to the control, status or result registers. 18.6.3 background d ebug (atd freeze) mode when debugging an applicati on, it is useful to have the atd pause when a breakpoint is enc ountered. to accommodate this, there are two freeze bits in the atdctl3 regist er used to select one of three responses: 1. the atd module may ignor e the freeze request. 2. it may respond to the freeze r equest by finish ing the current conversion and ?freezing? before starting the next sample period. 3. it may respond by im mediately ?freezing?. control and timing logic is static al lowing the register contents and timing position to be remembered indefinitel y. the analog electronics remains powered up; however, internal le akage may compromise the accuracy of a frozen conversion depending on the l ength of the freeze period. when the bdm signal is negated clock ac tivity resumes. access to the atd register file is possible during the ?frozen? period. 18.6.4 module reset the atd module is reset on two different events. 1. in the case of a system reset. 2. if the rst bit in the atdtest regist er is activated. the single difference between the two events is t hat the rst bit event does not reset the adpu bit to its rese t state value - i. e. the module is not reset into a powered down state a nd will be returned to an idle state.
analog-to-digital converter general purpose digital input port operation mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor analog-to-digital converter 357 the atd module reset function pl aces the module back into an initialized state. if the module is performing a conv ersion sequence, both the current conversion and t he sequence are te rminated. the conversion complete flags are cl eared and any pending interrupts are cancelled. note that the control, test, and status registers are initialized on reset; the initia lized register state is defi ned in the register description section of this specification. note that when the mo dule powers up via a wait signal that the atd is not reset; atd operation proceeds as it was prior to entering the wait. freezing the module does no t cause it to be reset. if a freeze mode is entered and defines that the current conversion be terminated, then this is done and the module will be idle afte r exiting the freeze state, but the module is not initialized. powering the module up (using the a dpu bit) does not cause the module to reset since the register file is not initialized. finally, writing to control register atdctl4/5 does not cause the module to be reset; the current conversion and sequence will be terminated and new ones started; the conversi on complete flags and pending interrupts will be cleared. this is a restart operation rather than a reset operation because the register file is not reinitialized. 18.7 general purpose digi tal input port operation there is one digital, 8-bit, inpu t-only port associated with the atd module. it is accessed through the 8- bit port data register (portadx). since the port pins are used only as inputs, in normal operating modes, no data direction r egister is availa ble for this port. the input channel pins ca n be used to read anal og and digital data. as analog inputs, they are mu ltiplexed and sampled to supply signals to the a/d converter. as digital inputs, they supply input data buffers that can be accessed through the digital port r egisters. analog signals present on the input pins at the digital sampling time t hat don?t meet the v il or v ih specification will return unknown digital values. a read of portadx may affect the accuracy of an in progress sample period but will not affect an in progress a/d conversion.
analog-to-digital converter technical data mc68hc9 12d60a ? rev. 3.1 358 analog-to-digital converter freescale semiconductor 18.8 application considerations note that the a/d converter?s accura cy is limited by the accuracy of the reference potentials. noise on the refer ence potentials will result in noise on the digital output dat a stream: the referenc e potential lines do not reject reference noise. the reference potential pins must have a low ac impedance path back to the source. a large bypass capacito r (100nf or larger) will suffice in most cases. in extreme cases, in ductors and/or ferr ite beads may be necessary if high frequency noise is present. series resistance is not advisable since the atd module draw s current from t he reference. a potential drop across any series resi stance would result in gain and offset errors in the digital data output stream unless the reference potential was sensed at the reference inpu t pin and any potential drop compensated for. for best performance, the analog inputs s hould have a low ac impedance at the input pins to shunt noi se current coupled onto the input node away from the a/d i nput. this can be acco mplished by placing a capacitor with good high frequency characteristi cs between the input pin and v ssa . the size of this capacitor is application dependent; larger capacitors will lower the ac imped ance and be more effective at shunting away noise cu rrent. however, the in put analog signal has its own dynamic characteristics which the a/d converter is being used to track. these, along with the source impedance of th e signal driver, must also be considered when choosing the c apacitor size to avoid rolling off any high frequency com ponents of interest. if the input signal contains exce ssive high frequen cy conducted noise, then a series resistance may be us ed with the capacitor to generate a one pole, low pass ant i-aliasing filter. 18.9 atd registers control and data register s for the atd modules are described below. both atds have identical control registers mapped in two blocks of 16 bytes.
analog-to-digital converter atd registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor analog-to-digital converter 359 18.9.1 atd control regist ers 0 &1 (atdctl0, atdctl1) writes to this register will abort current conversion sequence. read or write any time. write: write to this register has no meaning. read: special mode only. 18.9.2 atd control regist ers 2 & 3 (atdctl2, atdctl3) the atd control registers 2 & 3 are used to select the power up mode, fast flag clear mode, wait mode, 16 channel mode, interr upt control, and freeze control. writes to these re gisters will not abo rt the current conversion sequence nor start a new sequence. read: any time write: any time (except for bit 0 ? ascif, read: any time, write: not allowed) adpu ? atd disable / power down 0 = disable and power down the atd 1 = normal atd functionality atd0ctl0/atd1ctl0 ? reserved $0060/$01e0 bit 7654321bit 0 reset: 00000000 atd0ctl1/atd1ctl1 ? reserved $0061/$01e1 bit 7654321bit 0 reset: 0 0 0 0 0 0 0 0 atd0ctl2/atd1ctl2 ? atd control register 2 $0062/$01e2 bit 7654321bit 0 adpu affc aswai djm reserved reserved ascie ascif reset: 0 0 0 0 0 0 0 0
analog-to-digital converter technical data mc68hc9 12d60a ? rev. 3.1 360 analog-to-digital converter freescale semiconductor this bit provides program on/off cont rol over the atd module allowing reduced mcu power consumption wh en the atd is not being used. when reset to zero, the adpu bit aborts any conversion sequence in progress. because the analog elec tronics is tur ned off when powered down, the atd requires a recovery time period wh en adpu bit is enabled. affc ? atd fast conversi on complete flag clear 0 = atd flag clearing operates nor mally (read the st atus register before reading the result regist er to clear the associated ccf bit). 1 = changes all atd co nversion complete flags to a fast clear sequence. any access to a result register (atd0?7) will cause the associated ccf flag to clear automatical ly if it was set at the time. operating normally means that the status register must be read after the conversion complete flag has been set before that flag can be reset. after the status register read, a read to the associated result register causes its conversion complete flag in the status register to be cleared. the scf flag is cleared when a new conversion sequence is begun by writing to control register atdctl4/5. in applications where the atd module is polled to determine if an atd conversion is complete, this feature provides a convenient way of clearing the status register conversion complete flag. in applications where atd interrupts are used to signal conversion completion, the precondition of read ing the status register can be eliminated using fast co nversion complete flag clear mode. in this mode, any access to a result regi ster will cause its associated conversion complete flag in the status register to be cleared. the scf flag is cleared after the first ( any) result register is read. aswai ? atd stop in wait mode 0 = atd continues to run wh en the mcu is in wait mode 1 = atd stops to save power when the mcu is in wait mode the wait function allows the mcu to selectiv ely halt and power down the atd module. if the aswai bit is set and the m cu, then the atd module immediately halts operation and powers down. when wait is
analog-to-digital converter atd registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor analog-to-digital converter 361 exited, the atd module powers up and continues operation. the module is not reset; the register file is not reinitialized; the conversion sequence is not restarted. when the module comes out of wa it, it is recommended that a stabilization delay ( t sr ) is allowed before new conversions are started. djm ? result register data justification mode 0 = left justified mode 1 = right ju stified mode for 10-bit resolution, left justifi ed mode maps a result register into data bus bits 6 through 15; bit 15 is the msb. in right justified mode, the result registers m aps onto data bus bits 0 through 9; bit 9 is the msb. for 8-bit resolution, left justified mode maps a result into the high byte (bits 8 though 15; bit 15 is the msb). ri ght justified maps a result into the low byte (bits 0 throu gh 7; bit 7 is the msb). table 18-1 summarizes the result dat a formats available and how they are set up usin g the control bits. table 18-2 illustrates left justified outp ut codes for an input signal range between 0 and 5.1 volts. res10 djm result data formats description and bus bit mapping 0 0 1 1 0 1 0 1 8-bit/left justified - bits 8-15 8-bit/right justified - bits 0-7 10-bit/left justified - bits 6-15 10-bit/right justified - bits 0-9 table 18-1. result data formats available
analog-to-digital converter technical data mc68hc9 12d60a ? rev. 3.1 362 analog-to-digital converter freescale semiconductor ascie ? atd sequence comp lete interrupt enable 0 = disables atd interrupt 1 = enables atd interr upt on sequence complete the sequence complete interrupt f unction signals th e mcu when a conversion sequence is complete. at this time, the result registers contain the result data generated by the conversion s equence. if this interrupt function is disabled, then the conversion complete flags must be polled to determine when a conv ersion or a conversion sequence is complete. note that reset clears pending interrupts. ascif ? atd sequence complete interrupt flag 0 = no atd sequence complete interrupt occurred 1 = atd sequence complete interrupt occurred the sequence complete inte rrupt flag. this flag is not cleared until the interrupt is serviced (by reading the result data in such a way that the conversion complete flag is clear ed), a new conversion sequence is initiated, or the module is reset. this bit is not wr itable in any mode. input signal vrl = 0 volts vrh = 5.12 volts 8-bit codes 10-bit codes 5.120 volts 5.100 5.080 2.580 2.560 2.540 0.020 0.000 ff ff fe 81 80 7f 01 00 ffc0 ff00 fe00 8100 8000 7f00 0100 0000 table 18-2. left justif ied atd output codes
analog-to-digital converter atd registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor analog-to-digital converter 363 read: any time write: any time s1c ? conversion sequence lengt h (least significant bit) this control bit works with control bit s8c in atdctl5 in determining how many conversion are performed per sequence. when the s1c bit is set, a sequenc e length of 1 is defined. however, if the s8c bit is also set, the s8c bit takes precedence. for sequence length coding information see the description for s8c bit in atdctl5. fifo ? result r egister fifo mode 0 = result registers maps to the conversion sequence 1 = result registers do not map to the conversion sequence in normal operation, the a/d conversion results map into the result registers based on the conversion se quence; the result of the first conversion appears in the fi rst result register, t he second result in the second result register, and so on. in fifo mode the result register counter is not reset at the beg inning or ending of a conversion sequence; conversion re sults are placed in consecutive result registers between sequences. the re sult register counter wraps around when it reaches the end of th e result register file. the conversion counter value in at dstat0 can be used to determine where in the result register file, the next conversion result will be placed. the results register coun ter is initialized to zero on three events: on reset, the beginni ng of a normal (non-fif o) conversion sequence, and the end of a normal (non-fifo) conversion sequenc e. therefore, the reset bit in regist er atdtest1 can be toggled to zero the result register counter; any sequence allowe d to complete normally will zero the result register counter; a new sequence (non-fifo) initiated with a write to atdctl4/5 followed by a write to atdctl3 to set the fifo bit will start a fifo s equence with the result register initialized. atd0ctl3/atd1ctl3 ? atd control register 3 $0063/$01e3 bit 7654321bit 0 0000s1cfifofrz1frz0 reset: 0 0 0 0 0 0 0 0
analog-to-digital converter technical data mc68hc9 12d60a ? rev. 3.1 364 analog-to-digital converter freescale semiconductor finally, which result registers hold valid data can be tracked using the conversion complete flags. fast fl ag clear mode may or may not be useful in a particular applic ation to track valid data. frz1, frz0 ? backgr ound debug freeze enable background debug freeze function al lows the atd mo dule to pause when a breakpoint is encountered. table 18-3 shows how frz1 and frz0 determine the atd?s response to a breakpoint. when bdm is deasserted, the atd module continue s operating as it was before the breakpoint occurred. 18.9.3 atdctl4 atd co ntrol register 4 atd control register 4 is used to se lect the internal atd clock frequency (based on the system clock) , select the length of the third phase of the sample period, and set the resolution of the a/d conversion (i.e. 8-bits or 10-bits). all writes to this regi ster have an immediate effect. if a conversion is in progre ss, the entire conversi on sequence is aborted. a write to this register (or atdctl5) initiates a new conversion sequence. table 18-3. atd response to background debug enable frz1 frz0 atd response 0 0 continue conversions in active background mode 01 reserved 1 0 finish current conversion, then freeze 1 1 freeze when bdm is active atd0ctl4/atd1ctl4 ? atd control register 4 $0064/$01e4 bit 7654321bit 0 res10 smp1 smp0 prs4 prs3 prs2 prs1 prs0 reset: 00000001
analog-to-digital converter atd registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor analog-to-digital converter 365 res10 ? a/d resolution select 0 = 8-bit reso lution selected 1 = 10-bit resolution selected this bit determines the re solution of the a/d conv erter: 8-bits or 10- bits. the a/d converter has the a ccuracy of a 10-bit converter. however, if low resolution is adequate, the conversion can be speeded up by select ing 8-bit resolution. smp[1:0] ? sample time select these two bits select the length of the third phase of the sample period (in internal atd cl ock cycles) which occurs after the buffered sample and transfer. during this phas e, the external analog signal is connected directly to t he storage node for final charging and improved accuracy. note that the atd clock period is itself a function of the prescaler value (bits prs0?4). table 18-4 lists the lengths available for the third sample phase. prs[4:0] ? atd clock prescaler the binary prescaler value (0 to 31 ) plus one (1 to 32) becomes the divide-by-factor for a modulus counter used to prescale the system pclk frequency. the resu lting scaled clock is further divided by 2 before the atd internal clock is gener ated. this clock is used to drive the s/h and a/d machines. note that the maximum atd clock frequency is half of the system clock. the default prescaler value is 00001 which resu lts in a default atd clock frequency that is quarter of the system clock i.e. with 8mhz bus the atd module clock is 2mhz. table 18-5 illustrates the divide- by operation and the appr opriate range of syst em clock frequencies. table 18-4. final sample time selection smp1 smp0 final sample time 0 0 2 a/d clock periods 0 1 4 a/d clock periods 1 0 8 a/d clock periods 1 1 16 a/d clock periods
analog-to-digital converter technical data mc68hc9 12d60a ? rev. 3.1 366 analog-to-digital converter freescale semiconductor 18.9.4 atdctl5 atd co ntrol register 5 atd control register 5 determines the type of conversion sequence and the analog input channels sampled. all writes to this register have an immediate effect. if a conversion is in progress, the entire conversion sequence is aborted. a write to this r egister (or atdctl4) initiates a new conversion sequence (scf an d ccf bits are reset). s8c / s1c ? conver sion sequence length s8c: bit position: 6, atdctl5 s1c: bit position: 3, atdctl3 the s8c/s1c bits define the l ength of a conv ersion sequence . table 18-6 lists the coding combinations. table 18-5. clock prescaler values prescale value total divisor max pclk (1) 1. maximum conversion frequency is 2 mhz. maximum pclk divisor value will become maximum conversion rate that can be used on this atd module. min pclk (2) 2. minimum conversion frequency is 500 khz. minimum pclk divisor value will become minimum conversion rate that this atd can perform. 00000 24 mhz 1 mhz 00001 48 mhz 2 mhz 00010 68 mhz 3 mhz 00011 88 mhz 4 mhz 00100 10 8 mhz 5 mhz 00101 12 8 mhz 6 mhz 00110 14 8 mhz 7 mhz 00111 16 8 mhz 8 mhz 01xxx do not use 1xxxx atd0ctl5/atd1ctl5 ? atd control register 5 $0065/$01e5 bit 7654321bit 0 0 s8c scan mult sc cc cb ca reset: 00000000
analog-to-digital converter atd registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor analog-to-digital converter 367 the result register assignments made to a conversion sequence follow a few simple rules. normally, the first result is placed in the first register; the second result is placed in the second register, and so on. table 18- 7 presents the result register assi gnments for the various conversion lengths that are normally made. if fifo mode is used, the result register assignments differ. the re sults are placed in consecutive registers between conversion sequence s; the result register mapping wraps around when the end of the register file is reached. scan ? continuous conv ersion sequence mode 0 = perform a conversion sequ ence and return to idle mode 1 = perform conversion sequences continuously (scan mode) the scan mode bit controls whether or not conversion sequences are performed continuously or not. if this c ontrol bit is 0, a write to control register 4 or 5 will initiate a conversion sequence; the conversion sequence will be executed; the sequenc e complete flag (scf) will be set, and the module will return to id le mode. in this mode, the module remains powered up bu t no conversions are per formed; the module waits for the next conversi on sequence to be initiated. if this control bit is 1, a single c onversion sequence initia tion will result in a continuously executed conver sion sequence. when a conversion sequence completes, t he sequence complete flag (scf) is set and a new sequence is immediatel y begun. the conversion mode characteristics of each sequence ar e identical. if a new conversion s8c s1c number of conversions per sequence 00 4 01 1 1x 8 table 18-6. conversion sequence length coding number of conversions per sequence result register assignment 1 adr0 4 adr0 through adr3 8 adr0 through adr7 table 18-7. result register assignme nt for different conversion sequences
analog-to-digital converter technical data mc68hc9 12d60a ? rev. 3.1 368 analog-to-digital converter freescale semiconductor mode is required, the existi ng continuous sequence must be interrupted, the control regist ers modified, and a new conversion sequence initiated. mult ? multi-channel sample mode 0 = sample only t he specified channel 1 = sample across many channels when mult is 0, the atd sequence controller samples only from the specified analog inpu t channel for an entir e conversion sequence. the analog channel is selected by channel selection code (control bits cc/cb/ca located in atdctl5). when mult is 1, the atd seq uence controller samples across channels. the number of channels sampled is determined by the sequence length va lue (s8c, s1c control bi ts). the first analog channel examined is determined by channel selection code (cc, cb, ca control bits); su bsequent channels sampled in the sequence are determined by incr ementing the channel selection code. sc ? special channel conversion mode 0 = perform a/d conversi on on an analog input channel 1 = perform special c hannel a/d conversion sc determines if the atd module performs a/d conversions on any of the analog input cha nnels (normal operation) or whether it performs a conversion on one of the defin ed, special channels. the special channels are normally used to te st the a/d machine and include converting the high and low refer ence potentials for the module. the control bits cc/cb/ca are used to indicate which special channel is to be converted. table 18-8. special channe l conversion select coding cc cb ca special expected channel digital result code 0xx reserved ? 100 vrh $ff 1 0 1 vrl $00 1 1 0 (vrh + vrl)/2 $7f 111 reserved ?
analog-to-digital converter atd registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor analog-to-digital converter 369 table 18-8 lists the special channels. th e last column in the table denote the expected digital c ode that should be generated by the special conversion fo r 8-bit resolution. cc, cb, ca ? analog input channel select code these bits select the analog input channel(s). table 18-9 lists the coding used to select the various analog input channels. in the case of single channel scans (mult=0), this selection code specifies the channel for conversion. in the case of multi-channel scans (mult=1), this selection code repr esents the first channel to be examined in the conversion sequence. subsequent channels are determined by incrementing the channel selection code; selection codes that reach the maximum value wrap ar ound to the minimum value. note that for special conversi on mode, bits cc/cb/ca have a different function. instead of spec ifying the analog i nput channel, they identify which special channel conv ersion is to take place. (see table 18-8 .) a summart of the channels converted and t he associated result locations for multiple cha nnel scans can be found in table 18-10 . table 18-9. analog input channel select coding cc cb ca analog input channel 000 ad0 001 ad1 010 ad2 011 ad3 100 ad4 101 ad5 110 ad6 111 ad7
analog-to-digital converter technical data mc68hc9 12d60a ? rev. 3.1 370 analog-to-digital converter freescale semiconductor table 18-10. multichannel mode r esult register a ssignment (mult=1) 4 channel conversion, external channels (s8c = 0, sc = 0) cc 0 000 1 111 cb 0 011 0 011 ca 0 101 0 101 adr0 an0 an1 an2 an3 an4 an5 an6 an7 adr1 an1 an2 an3 an4 an5 an6 an7 an0 adr2 an2 an3 an4 an5 an6 an7 an0 an1 adr3 an3 an4 an5 an6 an7 an0 an1 an2 s1c bit must be clear. 4 channel conversion, internal sources (s8c = 0, sc = 1) cc0000 1 111 cb0011 0 011 ca0101 0 101 adr0 vrh vrl mid adr1 vrh vrl mid adr2 vrh vrl mid adr3 vrh vrl mid shaded cells are reserved mid = (vrh + vrl) / 2 s1c bit must be clear.
analog-to-digital converter atd registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor analog-to-digital converter 371 8 channel conversion, external channels (s8c = 1, sc = 0) cc 0 0001111 cb 0 0110011 ca 0 1010101 adr0 an0 an1 an2 an3 an4 an5 an6 an7 adr1 an1 an2 an3 an4 an5 an6 an7 an0 adr2 an2 an3 an4 an5 an6 an7 an0 an1 adr3 an3 an4 an5 an6 an7 an0 an1 an2 adr4 an4 an5 an6 an7 an0 an1 an2 an3 adr5 an5 an6 an7 an0 an1 an2 an3 an4 adr6 an6 an7 an0 an1 an2 an3 an4 an5 adr7 an7 an0 an1 an2 an3 an4 an5 an6 8 channel conversion, internal sources (s8c = 1, sc = 1) cc 0 0001111 cb 0 0110011 ca 0 1010101 adr0 vrh vrl mid adr1 vrh vrl mid adr2 vrh vrl mid adr3 vrh vrl mid adr4 vrh vrl mid adr5 vrl mid vrh adr6 mid vrh vrl adr7 vrh vrl mid shaded cells are reserved mid = (vrh + vrl) / 2 notes: 1) for compatibility with the 68hc912d60, ca, cb, cc bits must be ?0? where masked on the 68hc912d60. this is shown above in bold text. 2) when mult = 0, all four bits (sc, cc, cb, and ca) must be specified and a conversion sequence consists of four or eight consecutive conversions of the single specified channel. 3) when s8c = 0 and s1c = 1, all four bits (sc, cc, cb, and ca) must be specified and a conversion sequence consists of one conversion of the single specified channel. table 18-10. multichannel m ode result register assi gnment (mult=1) (continued)
analog-to-digital converter technical data mc68hc9 12d60a ? rev. 3.1 372 analog-to-digital converter freescale semiconductor 18.9.5 atdstat a/ d status register the atd status registers contain t he conversion complete flags and the conversion sequence counter. the status registers are read-only . scf ? sequence complete flag this flag is set upon completion of a conversion sequence. if conversion sequences are continuous ly performed (scan=1), the flag is set after each one is comp leted. how this flag is cleared depends on the setting of the fast flag clear bit. when affc=0, scf is cleared when a new conversion sequence is initia ted (write to register atdctl4/5). when affc=1 , scf is cleared after reading the first (any) result register. cc[2:0] ? conversion counter this 3-bit value represents the contents of the re sult register counter; the result register counter points to the result re gister that will receive the result of the current conversion. if not in fifo m ode, the register counter is initialized to zero when a new conv ersion sequence is begun. if in fifo mode, the register c ounter is not init ialized. the result register count wraps around when its maximum value is reached. ccf[7:0] ? conversi on complete flags a conversion complete flag is set at the end of each conversion in a conversion sequence. the flags are a ssociated with the conversion position in a sequence and the result regist er number. therefore, ccf0 is set when the first conversi on in a sequence is complete and atd0stat0/atd1stat0 ? atd status register $0066/$01e6 bit 7654321bit 0 scf 0 0 0 0 cc2 cc1 cc0 reset:00000000 atd0stat1/atd1stat1 ? atd status register $0067/$01e7 bit 7654321bit 0 ccf7 ccf6 ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 reset: 0 0 0 0 0 0 0 0
analog-to-digital converter atd registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor analog-to-digital converter 373 the result is available in result register adr0; ccf 1 is set when the second conversion in a sequence is complete and the result is available in adr1, and so forth. the conversion complete flags are cleared depending on the setting of the fast flag cl ear bit (affc in atdctl2). when affc=0, the status register containing the conv ersion complete flag must be read as a precondition before t he flag can be cleared. t he flag is actually cleared during a subsequent access to the result register. this provides a convenient method for clearing the conv ersion complete flag when the user is polling the atd module; it ensures the user is signaled as to the avai lability of new data and avoids having to have the user clear t he flag explicitly. when affc=1, the conversion comple te flags are cleared when their associated result registers are read; reading the status register is not a necessary condition in order to clear them. this is the easiest method for cleari ng the conversion complete flags which is useful when the atd module signals conversion completion with an interrupt. the conversion complete flags are norm ally read only; in special (test) mode they can be written. note: when atdctl4/5 register is written, the scf fl ags and all ccfx flags are cleared; any pending interr upt request is canceled.
analog-to-digital converter technical data mc68hc9 12d60a ? rev. 3.1 374 analog-to-digital converter freescale semiconductor 18.9.6 atdtest module tes t register (atdtest) the test registers implement various special (test) modes used to test the atd module. the re set bit in atdtest1 is always read/write . the sar (successive approxi mation register) can a lways be read but only written in special (test) mode. the functions implemented by the test registers are reserved for factory test. sar[9:0] ? successive approximation register this ten bit value represents t he contents of t he ad machine?s successive approximation register. this value can always be read. it can only be written in special (t est) mode. note that atdtest0 acts as a ten bit register since the entire sar is read/written when accessing this address. rst ? test mode reset bit 0 = no reset 1 = reset the atd module when set, this bit causes the atd m odule to reset itself. this sets all registers to their reset state (note the reset stat e of the reset bit is zero), the current conversion and conversion sequenc e are aborted, pending interrupts are clear ed, and the module is placed in an idle mode. atd0testh/atd1testh ? atd test register $0068/$01e8 bit 7654321bit 0 sar9 sar8 sar7 sar6 sar5 sar4 sar3 sar2 reset: 0 0 0 0 0 0 0 0 atd0testl/atd1testl ? atd test register $0069/$01e9 bit 7654321bit 0 sar1 sar0 rst 0 0 0 0 0 reset: 0 0 0 0 0 0 0 0
analog-to-digital converter atd registers mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor analog-to-digital converter 375 resetting to idle mode defines the onl y exception of the reset control bit condition to the system reset c ondition. the reset control bit does not initialize the adpu bit to its reset condition and therefore does not power down the module. this except allows the module to remain active for other test operations. 18.9.7 portad port data register the input data port associated with the atd module is input-only. the port pins are shared wi th the analog a/d inputs. padx[7:0] ? port ad data input bits reset: these pins reflect t he state of the input pins. the atd input ports may be used for general purpose digital input. when the port data registers are read, they contain the digital levels appearing on the input pins at the time of the r ead. input pins with signal potentials not meeting v il or v ih specifications will have an indeterminate value. use of any port pin for digital inpu t does not preclude the use of any other port pin for analog input. writes to this register have no meaning at any time. portad0/portad1 ? port ad data input register $006f/$01ef bit 7654321bit 0 padx7 padx6 padx5 padx4 padx3 padx2 padx1 padx0 reset: - - ------
analog-to-digital converter technical data mc68hc9 12d60a ? rev. 3.1 376 analog-to-digital converter freescale semiconductor 18.9.8 adrx a/d conversion result registers (adr0-15) the a/d conversion result s are stored in 8 resu lt registers. these registers are designat ed adr0 through adr7. the result data is formatted using t he djm control bit in atdctl2. for 8-bit result data, the result data ma ps between the high (l eft justified) and low (right justified) order bytes of the result r egister. for 10-bit result data, the result data maps between bits 6-15 (left justif ied) and bits 0-9 (right justified) of the result register. these registers are normally read-only. adrx0h ? a/d converter result register 0 $0070/$01f0 adrx0l ? a/d converter result register 0 $0071/$01f1 adrx1h ? a/d converter result register 1 $0072/$01f2 adrx1l ? a/d converter result register 1 $0073/$01f3 adrx2h ? a/d converter result register 2 $0074/$01f4 adrx2l ? a/d converter result register 2 $0075/$01f5 adrx3h ? a/d converter result register 3 $0076/$01f6 adrx3l ? a/d converter result register 3 $0077/$01f7 adrx4h ? a/d converter result register 4 $0078/$01f8 adrx4l ? a/d converter result register 4 $0079/$01f9 adrx5h ? a/d converter result register 5 $007a/$01fa adrx5l ? a/d converter result register 5 $007b/$01fb adrx6h ? a/d converter result register 6 $007c/$01fc adrx6l ? a/d converter result register 6 $007d/$01fd adrx7h ? a/d converter result register 7 $007e/$01fe adrx7l ? a/d converter result register 7 $007f/$01ff adrxxh bit 15654321bit 8 adrxxl bit 7bit 6000000 reset: 00000000
mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor development support 377 technical data ? mc68hc912d60a section 19. development support 19.1 contents 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 19.3 instruction queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377 19.4 background debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 19.5 breakpoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 19.6 instruction tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 19.2 introduction development support involves complex intera ctions between mc68hc912d60a resources and exter nal development systems. the following section concerns instruction queu e and queue tracking signals, background debug mode, and instruction tagging. 19.3 instruction queue the cpu12 instructio n queue provides at least three bytes of program information to the cpu when instru ction execution b egins. the cpu12 always completely finishes executi ng an instruction before beginning to execute the next instruction. st atus signals ipipe[1:0] provide information about data movement in the queue and indicate when the cpu begins to execute instructions. this makes it possible to monitor cpu activity on a cycle-by-cycle basis for debugging. information available on the ipipe[1:0] pins is time multiplexed. external circuitry can latch data movement inform ation on rising edge s of the eclk signal; execution start informat ion can be latched on falling edges. table 19-1 shows the meaning of data on the pins.
development support technical data mc68hc9 12d60a ? rev. 3.1 378 development support freescale semiconductor program information is fetched a few cycl es before it is used by the cpu. in order to monitor cyc le-by-cycle cpu activity, it is necessary to externally reconstruc t what is happening in the instruction queue. internally the mcu only needs to buffer the data from program fetches. for system debug it is necessary to keep the data and its associated address in the reconstructed inst ruction queue. the raw signals required for reconstruction of the queue are addr, data, r/w , eclk, and status signals ipipe[1:0]. the instruction queue consists of tw o 16-bit queue stages and a holding latch on the input of the first st age. to advance the queue means to move the word in the first stage to the second stage and move the word from either the holding latch or t he data bus input buffe r into the first stage. to start even (or odd) instruct ion means to exec ute the opcode in the high-order (or low-orde r) byte of the second st age of the instruction queue. table 19-1. ipipe decoding data movement ? ipipe[1:0] captured at rising edge of e clock (1) 1. refers to data that was on the bus at the previous e falling edge. ipipe[1:0] mnemonic meaning 0:0 ? no movement 0:1 lat latch data from bus 1:0 ald advance queue and load from bus 1:1 all advance queue and load from latch execution start ? ipipe[1:0] captured at falling edge of e clock (2) 2. refers to bus cycle starti ng at this e falling edge. ipipe[1:0] mnemonic meaning 0:0 ? no start 0:1 int start interrupt sequence 1:0 sev start even instruction 1:1 sod start odd instruction
development support background debug mode mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor development support 379 19.4 background debug mode background debug mode (b dm) is used for syst em development, in- circuit testing, field testing, and programming. bdm is implemented in on-chip hardware and provides a full set of debug options. because bdm control logic does not reside in the c pu, bdm hardware commands can be executed while t he cpu is operating normally. the control logic generally uses free cpu cycles to execute these commands, but can steal cycles fro m the cpu when necessary. other bdm commands are firmware based, and r equire the cpu to be in active background mode for executio n. while bdm is acti ve, the cpu executes a firmware program located in a sma ll on-chip rom that is available in the standard 64-kbyte me mory map only while bdm is active. the bdm control logic communicates with an external host development system serially, via the bkgd pin. this single-wire approach minimizes the number of pins needed for development support. 19.4.1 enabling bdm firmware commands bdm is available in all operating mo des, but must be made active before firmware commands can be executed. bdm is enabled by setting the enbdm bit in the bdm st atus register via t he single wire interface (using a hardware command; writ e_bd_byte at $ff01). bdm must then be activated to map bdm r egisters and rom to addresses $ff00 to $ffff and to put the mcu in active background mode. after the firmware is enabled, bdm can be acti vated by the hardware background command, by the bdm tagging me chanism, or by the cpu bgnd instruction. an attempt to activate bdm before firmware has been enabled causes the mcu to resu me normal instruction execution after a brief delay. bdm becomes active at the nex t instruction b oundary following execution of the bdm background command, but tags activate bdm before a tagged instru ction is executed.
development support technical data mc68hc9 12d60a ? rev. 3.1 380 development support freescale semiconductor in special single-chip mode, backg round operation is enabled and active immediately out of reset. this active case replaces the m68hc11 boot function, and allows programming a system with blank memory. while bdm is active, a set of bd m control regist ers are mapped to addresses $ff00 to $ff06. the bdm control logic us es these registers which can be read anytime by bdm logi c, not user programs. refer to bdm registers for detailed descriptions. some on-chip peripherals have a bdm control bit which allows suspending the peripheral function duri ng bdm. for example, if the timer control is enabled, the timer count er is stopped while in bdm. once normal program flow is continued, the timer c ounter is re-enabled to simulate real-time operations. 19.4.2 bdm serial interface the bdm serial interface requires the external controller to generate a falling edge on the bkgd pin to indicate the st art of each bi t time. the external controller provides this fa lling edge whether data is transmitted or received. bkgd is a pseudo-open-drain pin t hat can be driven either by an external controller or by the mcu. data is transferred msb first at 16 bdmclk cycles per bit ( nominal speed). the inte rface times out if 512 bdmclk cycles occur between fa lling edges from the host. the hardware clears the co mmand register when a time-out occurs. the bkgd pin can receive a high or lo w level or transmi t a high or low level. the following diagrams show ti ming for each of these cases. interface timing is synchronous to m cu clocks but asynch ronous to the external host. the internal clock signal is shown for reference in counting cycles. figure 19-1 shows an external host transmitt ing a logic one or zero to the bkgd pin of a target mc 68hc912d60a mcu. the host is asynchronous to the target so there is a 0-to-1 cycle del ay from the host- generated falling edge to wher e the target perceives the beginning of the bit time. ten target b cycles later, the target sens es the bit level on the bkgd pin. typically the host acti vely drives the pseudo-open-drain
development support background debug mode mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor development support 381 bkgd pin during host-to-target tran smissions to speed up rising edges. since the target does not drive the bkgd pi n during this period, there is no need to treat the line as an open-drain signal during host-to-target transmissions. figure 19-1. bdm host to target serial bit timing figure 19-2. bdm target to h ost serial bit timing (logic 1) 10 cycles bdmclk (target mcu) host transmit 1 target senses bit earliest start of next bit synchronization uncertainty perceived start of bit time host transmit 0 10 cycles bdmclk (target mcu) earliest start of next bit bkgd pin perceived start of bit time 10 cycles host samples bkgd pin host drive to bkgd pin target mcu speedup pulse r-c rise high-impedance high-impedance high-impedance
development support technical data mc68hc9 12d60a ? rev. 3.1 382 development support freescale semiconductor figure 19-2 shows the host receiving a logic one from the target mc68hc912d60a mcu. since the host is asynchronous to the target mcu, there is a 0-to-1 cycle delay from t he host-generated falling edge on bkgd to the perceived st art of the bit time in the target mcu. the host holds the bkgd pin low long enough for the ta rget to recognize it (at least two target b cycl es). the host must rel ease the low drive before the target mcu drives a brief ac tive-high speed-up pulse seven cycles after the perceived start of the bit time. the host should sample the bit level about ten cycles afte r it started the bit time. figure 19-3. bdm target to h ost serial bit timing (logic 0) figure 19-3 shows the host receiving a logic zero from the target mc68hc912d60a mcu. since the host is asynchronous to the target mcu, there is a 0-to-1 cycle delay from t he host-generated falling edge on bkgd to the start of th e bit time as perceived by the target mcu. the host initiates the bit time but the target mc68hc912d 60a finishes it. since the target wants t he host to receive a logi c zero, it drives the bkgd pin low for 13 bdmc lk cycles, then briefly dr ives it high to speed up the rising edge. the host samples the bit leve l about ten cycles after starting the bit time. 10 cycles bdmclk (target mcu) earliest start of next bit bkgd pin perceived start of bit time 10 cycles host samples bkgd pin host drive to bkgd pin target mcu drive and speedup pulse high-impedance speedup pulse
development support background debug mode mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor development support 383 19.4.3 bdm commands the bdm command set consists of tw o types: hardware and firmware. hardware commands allow target system memory to be read or written. target system memory includes all me mory that is accessible by the cpu12 including eepro m, on-chip i/o and c ontrol registers, and external memory that is connected to the target hc 12 mcu. hardware commands are implemented in hard ware logic and do not require the hc12 mcu to be in bdm mode for exec ution. the control logic watches the cpu12 buses to find a free bus cycl e to execute the command so the background access does not disturb t he running applicat ion programs. if a free cycle is not found with in 128 bdmclk cycles , the cpu12 is momentarily frozen so th e control logic can st eal a cycle. commands implemented in bdm contro l logic are listed in table 19-2 .
development support technical data mc68hc9 12d60a ? rev. 3.1 384 development support freescale semiconductor the second type of bdm comma nds are firmware commands implemented in a small rom within the hc12 mcu. the cpu must be in background mode to execute fi rmware commands. the usual way to get to background mode is by th e hardware command background. the bdm rom is located at $ff20 to $ffff while bdm is active. there are also seven bytes of bdm regi sters located at $ff00 to $ff06 when bdm is active. the cpu executes code in the bdm firmware to perform the requested operation. the bdm firmware watches for serial commands and executes them as th ey are received. the firmware commands are shown in table 19-3 . table 19-2. hardware commands (1) command opcode (hex) data description background 90 none enter background mode if firmware enabled. read_bd_byte (1) e4 16-bit address 16-bit data out read from memory with bdm in map (may steal cycles if external access) data for odd address on low byte, data for even address on high byte. read_bd_word (1) ec 16-bit address 16-bit data out read from memory with bdm in map (may steal cycles if external access). must be aligned access. read_byte e0 16-bit address 16-bit data out read from memory with bdm out of map (may steal cycles if external access) data for odd address on low byte, data for even address on high byte. read_word e8 16-bit address 16-bit data out read from memory with bdm out of map (may steal cycles if external access). must be aligned access. write_bd_byte (1) c4 16-bit address 16-bit data in write to memory with bdm in map (may steal cycles if external access) data for odd address on low byte, data for even address on high byte. write_bd_word (1) cc 16-bit address 16-bit data in write to memory with bdm in map (may steal cycles if external access). must be aligned access. write_byte c0 16-bit address 16-bit data in write to memory with bdm out of map (may steal cycles if external access) data for odd address on low byte, data for even address on high byte. write_word c8 16-bit address 16-bit data in write to memory with bdm out of map (may steal cycles if external access). must be aligned access. 1. use these commands only for reading/writing to bdm locations . the bdm firmware rom and bdm registers are not nor- mally in the hc12 mcu memory map . since these locations have the same addresses as some of the normal application memory map, there needs to be a way to decide which ph ysical locations are being accessed by the hardware bdm commands . this gives rise to needing separate memory access commands for the bdm locations as opposed to the normal application locations . in logic, this is accomplished by momentaril y enabling the bdm memory resources, just for the access cycles of the read_bd and write_bd commands . this logic allows the debu gging system to unobtrusively access the bdm locations even if the application program is r unning out of the same memory area in the normal appli- cation memory map .
development support background debug mode mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor development support 385 each of the hardware a nd firmware bdm commands start with an 8-bit command code (opcode). depending upon the commands, a 16-bit address and/or a 16-bit data word is required as indicate d in the tables by the command. all the read comm ands output 16-bits of data despite the byte/word implicat ion in the command name. the external host should wait 150 bdmclk cycles for a non-intrusive bdm command to execut e before another command is sent. this delay includes 128 bdmclk cycles for the maximum delay for a free cycle. for data read commands, the host must insert this delay between sending the address and attemp ting to read the data. in the case of a write command, t he host must delay after the data portion before sending a new command to be sure that the write has finished. the external host should delay about 32 target bdmclk cycles between a firmware read command and the dat a portion of these commands. this allows the bdm firmware to execut e the instructions needed to get the requested data into the bdm shifter register. table 19-3. bdm firmware commands command opcode (hex) data description read_next 62 16-bit data out x = x + 2; read next word pointed to by x read_pc 63 16-bit data out read program counter read_d 64 16-bit data out read d accumulator read_x 65 16-bit data out read x index register read_y 66 16-bit data out read y index register read_sp 67 16-bit data out read stack pointer write_next 42 16-bit data in x = x + 2; write next word pointed to by x write_pc 43 16-bit data in write program counter write_d 44 16-bit data in write d accumulator write_x 45 16-bit data in write x index register write_y 46 16-bit data in write y index register write_sp 47 16-bit data in write stack pointer go 08 none go to user program trace1 10 none execute one user instruction then return to bdm taggo 18 none enable tagging and go to user program
development support technical data mc68hc9 12d60a ? rev. 3.1 386 development support freescale semiconductor the external host should delay about 32 target bdmclk cycles after the data portion of firmware write co mmands to allow bd m firmware to complete the requested write operation before a new serial command disturbs the bdm shifter register. the external host should delay about 64 target bdmclk cycles after a trace1 or go command bef ore starting any new serial command. this delay is needed because the bdm shifter regi ster is used as a temporary data holding regi ster during the exit sequence to user code. bdm logic retains control of the internal buses unt il a read or write is completed. if an operati on can be completed in a si ngle cycle, it does not intrude on normal cpu12 oper ation. however, if an operation requires multiple cycles, cpu12 cloc ks are frozen until the operation is complete. 19.4.4 bdm lockout the access to the mcu resources by bdm may be prevented by enabling the bdm lockout feature. when enabled, the bdm lockout mechanism prevents the bdm from being active. in this case the bdm rom is disabled and does not app ear in the mcu memory map. bdm lockout is enabled by clearing nobdml bi t of eemcr register. the nobdml bit is loaded at reset from the shadow byte of eeprom module. modifying t he state of the nobd ml and corresponding eeprom shadow bit is only possible in special modes. please refer to eeprom memory for nobdml information. 19.4.4.1 enabling bdm lockout enabling the bdm lockout feature is only possi ble in special modes (smodn=0) and is accompli shed by the following steps. 1. remove the shadow byte prot ection by clearing shprot bit in eeprot register. 2. clear noshb bit in eemcr regi ster to make the shadow byte visible at $0fc0. 3. program bit 7 of the shadow byte like a regular eeprom location at address $0fc0 (wri te $7f into address $0fc0). do not
development support background debug mode mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor development support 387 program other bits of the shadow byte (location $0fc0); otherwise some regul ar eeprom array loca tions will not be visible. at the next reset, the shadow byte is loaded into the eemcr register. nobdml bit in eemcr will be cleared and bdm will not be operational. 4. protect the shadow byte by setting shprot bit in eeprot register. 19.4.4.2 disabling bdm lockout disabling the bdm lock out is only possible in special modes (smodn=0) except in special single chip mode. follow the same steps as for enabling the bdm lockou t, but erase the shadow byte. at the next reset, the shadow byte is loaded into the eemcr register. nobdml bit in eemcr will be se t and bdm becomes operational. note: when the bdm lockout is enabled it is not possible to run code from the reset vector in spec ial single chip mode. 19.4.5 bdm registers seven bdm registers ar e mapped into the st andard 64-kbyte address space when bdm is active . mapping is shown in table 19-4 . the instruction register content is determined by the type of background command being executed. the status register indicate s bdm operating conditions. the shift register contains data being received or transmitted via the serial interface. table 19-4. bdm registers address register $ff00 bdm instruction register $ff01 bdm status register $ff02 - $ff03 bdm shift register $ff04 - $ff05 bdm address register $ff06 bdm ccr holding register
development support technical data mc68hc9 12d60a ? rev. 3.1 388 development support freescale semiconductor the address register is temporary storage for bdm commands. the ccrsav register preserves the content of the cpu12 ccr while bdm is active. the only registers of interest to us ers are the status register and the ccrsav register. the other bdm regi sters are only used by the bdm firmware to execute commands. the registers are accessed by means of the hardware read_bd and write_bd commands, but should not be written during bdm operation (exce pt the ccrsav re gister which could be written to m odify the ccr value). 19.4.5.1 status the status register is read and writ ten by the bdm hardware as a result of serial data sh ifted in on the bkgd pin. read: all modes. write: bits 3 through 5, and bit 7 are writable in all modes. bit 6, bdmact, can only be writt en if bit 7 h/f in the instruction register is a zero. bit 2, clksw, can only be written if bi t 7 h/f in the instruction register is a one. a user would nev er write ones to bits 3 through 5 because these bits ar e only used by bdm firmware. enbdm ? enable bdm (permit active background debug mode) 0 = bdm cannot be made active (hardw are commands still allowed). 1 = bdm can be made active to allow firmware commands. bit 7654321bit 0 enbdm bdmact entag sdv trace clksw - - reset: 0 (note 1) 1000000 special sin- gle chip & periph reset: 00000000 all other modes status? bdm status register (1) $ff01 1. enbdm is set to 1 by the firmware in special single chip mode.
development support background debug mode mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor development support 389 bdmact ? background mode active status bdmact becomes set as active bdm mode is entered so that the bdm firmware rom is enabled and put into the map. bdmact is cleared by a carefully ti med store instruction in the bdm firmware as part of the exit sequenc e to return to user code and remove the bdm memory from the map. this bit has 4 clock cycles write delay. 0 = bdm is not active. bdm ro m and registers are not in map. 1 = bdm is active and waiting for serial comm ands. bdm rom and registers are in map the user should be careful that the state of the bdmact bit is not unintentionally chan ged with the write_next firmware command. if it is unintentionally changed from 1 to 0, it will cause a system runaway because it would disable the bdm firmware rom while the cpu12 was executing bdm firm ware. the following two commands show how bdmact may unintenti onally get changed from 1 to 0. write_x with data $fefe write_next with data $c400 the first command writes the data $fe fe to the x index register. the second command writes the data $c4 to the $ff00 instruction register and also writ es the data $00 to the $ff01 status register. entag ? tagging enable set by the taggo command and cleared when bdm mode is entered. the serial system is di sabled and the tag function enabled 16 cycles after this bit is written. 0 = tagging not enabled, or bdm active. 1 = tagging active. bdm cannot pr ocess serial commands while tagging is active. sdv ? shifter data valid shows that valid data is in the serial interface shift r egister. used by the bdm firmware. 0 = no valid data. shift op eration is not complete. 1 = valid data. shift operation is complete. trace ? asserted by the trace1 command
development support technical data mc68hc9 12d60a ? rev. 3.1 390 development support freescale semiconductor clksw ? bdmclk clock switch 0 = bdm system op erates with bclk. 1 = bdm system op erates with eclk. the write_bd_byte@ff01 command that changes clksw including 150 cycles af ter the data portion of the command should be timed at the old speed. beginning with the start of the next bdm command, the new clock can be used for timing bdm communications. if eclk rate is slower than bd mclk rate, clksw is ignored and bdm system is forced to operate with eclk. 19.4.5.2 instruction - ha rdware instruction decode the instruction register is written by the bdm hardware as a result of serial data shifted in on the bkgd pin. it is readable and writable in special peripheral mode on the parallel bus. it is discussed here for two conditions: when a hardware command is executed and when a firmware command is executed. read and writ e: all modes the hardware clears the instruction register if 512 bdmclk cycles occur between falling edg es from the host. the bits in the bdm inst ruction register have the foll owing meanings when a hardware command is executed. h/f ? hardware /firmware flag 0 = firmware command 1 = hardware command bit 7654321bit 0 h/f data r/w bkgnd w/b bd/u 0 0 reset: 00000000 instruction ? bdm instruction register (hardware command explanation) $ff00
development support background debug mode mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor development support 391 data ? data flag - shows that data acco mpanies the command. 0 = no data 1 = data follows the command r/w ? read/write flag 0 = write 1 = read bkgnd ? hardware request to enter active background mode 0 = not a hardware background command 1 = hardware background co mmand (instruction = $90) w/b ? word/byte transfer flag 0 = byte transfer 1 = word transfer bd/u ? bdm map/user map flag indicates whether bdm register s and rom are mapped to addresses $ff00 to $ffff in the standard 64-kb yte address space. used only by hardware read/ write commands. 0 = bdm resources not in map 1 = bdm rom and registers in map the bits in the bdm inst ruction register have the foll owing meanings when a firmware command is executed. h/f ? hardware /firmware flag 0 = firmware command 1 = hardware command data ? data flag - shows that data acco mpanies the command. 0 = no data 1 = data follows the command bit 7654321bit 0 h/f data r/w ttago regn instruction ? bdm instruction register (firmware command bit explanation) $ff00
development support technical data mc68hc9 12d60a ? rev. 3.1 392 development support freescale semiconductor r/w ? read/write flag 0 = write 1 = read ttago ? trace, tag, go field regn ? regist er/next field indicates which register is being a ffected by a command. in the case of a read_next or wr ite_next command, index register x is pre-incriminated by 2 and the word pointed to by x is then read or written. table 19-5. ttago decoding table 19-6ttago value table 19-7instruction 00 ? 01 go 10 trace1 11 taggo table 19-8. regn decoding regn value instruction 000 ? 001 ? 010 read/write next 011 pc 100 d 101 x 110 y 111 sp
development support background debug mode mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor development support 393 19.4.5.3 shifter this 16-bit shift register contains dat a being received or transmitted via the serial interface. it is also us ed by the bdm firmware for temporary storage. read: all modes (but not normally accessed by users) write: all modes (but not normally accessed by users) bit 15 14 13 12 11 10 9 bit 8 s15 s14 s13 s12 s11 s10 s9 s8 reset: xxxxxxxx shifter? bdm shift register - high byte $ff02 bit 7654321bit 0 s7 s6 s5 s4 s3 s2 s1 s0 reset: xxxxxxxx shifter? bdm shift register - low byte $ff03
development support technical data mc68hc9 12d60a ? rev. 3.1 394 development support freescale semiconductor 19.4.5.4 address this 16-bit address register is temporary storage for bdm hardware and firmware commands. read: all modes (but not normally accessed by users) write: only by bdm har dware (state machine) bit 15 14 13 12 11 10 9 bit 8 a15 a14 a13 a12 a11 a10 a9 a8 reset: xxxxxxxx address? bdm address register - high byte $ff04 bit 7654321bit 0 a7 a6 a5 a4 a3 a2 a1 a0 reset: xxxxxxxx address? bdm address register - low byte $ff05
development support breakpoints mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor development support 395 19.4.5.5 ccrsav the ccrsav register is us ed to save the ccr of the users program when entering bdm. it is also used for tem porary storage in the bdm firmware. read and writ e: all modes 19.5 breakpoints hardware breakpoints are us ed to debug software on the mc68hc912d60a by comparing actual address and data values to predetermined data in set up registers. a successf ul comparison will place the cpu in backgr ound debug mode ( bdm) or initiate a software interrupt (swi). breakpoint features designed into the mc68hc912d60a include: mode selection for bdm or swi generation program fetch tagging for cycl e of execution breakpoint second address compar e in dual address modes range compare by disabl e of low byte address data compare in full featur e mode for non-tagged breakpoint byte masking for high/lo w byte data compares r/w compare for non-tagged compares tag inhibit on bdm trace bit 7654321bit 0 ccr7 ccr6 ccr5 ccr4 ccr3 ccr2 ccr1 ccr0 reset: note 1 (1) xxxxxxxx ccrsav? bdm ccr holding register $ff06 1. initialized to equal the cpu12 ccr register by the firmware.
development support technical data mc68hc9 12d60a ? rev. 3.1 396 development support freescale semiconductor 19.5.1 breakpoint modes three modes of oper ation determine the type of breakpoint in effect. dual address-only breakpoints, each of which will cause a software interrupt (swi) single full-feature breakpoint whic h will cause the part to enter background debug mode (bdm) dual address-only break points, each of which will cause the part to enter bdm breakpoints will not occu r when bdm is active. 19.5.1.1 swi d ual address mode in this mode, dual addr ess-only breakpoints can be set, each of which cause a software interr upt. this is the only breakpoint mode which can force the cpu to execute a swi. pr ogram fetch tagging is the default in this mode; data breakpoi nts are not possible. in the dual mode each address breakpoint is affected by the bkpm bit and the bkale bit. the bkxrw and bkxrwe bi ts are ignored. in dual address mode the bkdbe becomes an enable for t he second address breakpoint. the bksz8 bit will have no effect when in a dual address mode. 19.5.1.2 bdm full breakpoint mode a single full feature breakpoint which causes the part to enter background debug mode. bdm mode may be entered by a breakpoint only if an internal si gnal from the bdm indi cates background debug mode is enabled. breakpoints are not allowed if t he bdm mode is already active. active mode means the cpu is executing out of the bdm rom. bdm should not be entered from a breakpoint unless the enable bit is set in the bdm. this is important because even if the enable bit in the bdm is negated the cpu actually does execute the bdm rom code. it checks the e nable and returns if not set. if the bdm is not serviced by the monitor then the breakpoint would be re-asserted when the bdm returns to normal cpu flow.
development support breakpoints mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor development support 397 there is no hardware to enforce restriction of breakpoint operation if the bdm is not enabled. 19.5.1.3 bdm dual address mode dual address-only breakpoi nts, each of which ca use the part to enter background debug mode. in the dual mode each addr ess breakpoint is affected, consistent across modes, by the bkpm bit, t he bkale bit, and the bkxrw and bkxrwe bits. in dual address mode the bkdbe becomes an enable for the second address breakpoint . the bksz8 bit will have no effect when in a d ual address mode. bdm mode may be entered by a breakpoint only if an inte rnal signal from the bdm indicates background debug mode is enabled. bkdbe will be used as an enable for the second address only breakpoint. breakpoints are not allowed if t he bdm mode is already active. active mode means the cpu is executing out of the bdm rom. bdm should not be entered from a breakpoint unless the enable bit is set in the bdm. this is important because even if the enable bit in the bdm is negated the cpu actually does execute the bdm rom code. it checks the e nable and returns if not set. if the bdm is not serviced by the monitor then the breakpoint would be re-asserted when the bdm returns to normal cpu flow. there is no hardware to enforce restriction of breakpoint operation if the bdm is not enabled. 19.5.2 breakpoint registers breakpoint operation consists of co mparing data in the breakpoint address registers (br kah/brkal) to the address bus and comparing data in the breakpoint data registers (brkdh/b rkdl) to the data bus. the breakpoint data registers can al so be compared to the address bus. the scope of comparison can be ex panded by ignoring the least significant byte of address or data matches. the scope of comparison can be limited to program data only by setting the bkpm bit in breakpoint control register 0.
development support technical data mc68hc9 12d60a ? rev. 3.1 398 development support freescale semiconductor to trace program flow, se tting the bkpm bit caus es address comparison of program data only. control bits ar e also available that allow checking read/write matches. read and write anytime. this register is used to c ontrol the breakpoint logic. bken1, bken0 ? break point mode enable bkpm ? break on program addresses this bit controls whether the breakpoi nt will cause a break on a match (next instruction boundary) or on a match that will be an executable opcode. data and non-executed opcodes cannot cause a break if this bit is set. this bit has no mean ing in swi dual address mode. the swi mode only performs program breakpoints. 0 = on match, br eak at the next instruction boundary 1 = on match, break if the match is an instruction that will be executed. this uses tagging as its breakpoi nt mechanism. bk1ale ? breakpoint 1 range control only valid in dual address mode. 0 = brkdl will not be used to compare to the address bus. 1 = brkdl will be used to co mpare to the address bus. bit 7654321bit 0 bken1 bken0 bkpm 0 bk1ale bk0ale 0 0 reset: 00000000 brkct0 ? breakpoint control register 0 $0020 table 19-9. breakpoint mode control bken1 bken0 mode selected brkah/l usage brkdh/l usage r/w range 0 0 breakpoints off ? ? ? ? 0 1 swi ? dual address mode address match address match no yes 1 0 bdm ? full breakpoint mode address match data match yes yes 1 1 bdm ? dual address mode address match address match yes yes
development support breakpoints mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor development support 399 bk0ale ? breakpoint 0 range control valid in all modes. 0 = brkal will not be used to compare to the address bus. 1 = brkal will be used to co mpare to the address bus. this register is read/ write in all modes. bkdbe ? enable data bus enables comparing of address or dat a bus values using the brkdh/l registers. 0 = the brkdh/l registers are not used in any comparison 1 = the brkdh/l regist ers are used to co mpare address or data (depending upon the mode selections bken1,0) bkmbh ? breakpoint mask high disables the comparing of the high byte of data when in full breakpoint mode. used in conjuncti on with the bkdbe bit (which should be set) 0 = high byte of data bus (bit s 15:8) are compared to brkdh 1 = high byte is not used in comparisons table 19-10. breakpoint address range control bk1ale bk0ale address range selected ? 0 upper 8-bit address only for full mode or dual mode bkp0 ? 1 full 16-bit address for full mode or dual mode bkp0 0 ? upper 8-bit address only for dual mode bkp1 1 ? full 16-bit address for dual mode bkp1 bit 7654321bit 0 0 bkdbe bkmbh bkmbl bk1rwe bk1rw bk0rwe bk0rw reset: 00000000 brkct1 ? breakpoint control register 1 $0021
development support technical data mc68hc9 12d60a ? rev. 3.1 400 development support freescale semiconductor bkmbl ? breakpoint mask low disables the matching of the low by te of data when in full breakpoint mode. used in conjuncti on with the bkdbe bit (which should be set) 0 = low byte of data bus (bits 7:0) are compared to brkdl 1 = low byte is not used in comparisons. bk1rwe ? r/w compare enable enables the comparison of the r/w signal to further specify what causes a match. this bit is not us eful in program breakpoints or in full breakpoint mode. this bit is used in conjun ction with a second address in dual address mode when bkdbe=1. 0 = r/w is not us ed in comparisons 1 = r/w is used in comparisons bk1rw ? r/w compare value when bk1rwe = 1, this bit determi nes the type of bus cycle to match. 0 = a write cycle w ill be matched 1 = a read cycle w ill be matched bk0rwe ? r/w compare enable enables the comparison of the r/w signal to further specify what causes a match. this bit is not useful in program breakpoints. 0 = r/w is not used in the comparisons 1 = r/w is used in comparisons bk0rw ? r/w compare value when bk0rwe = 1, this bit determines the type of bus cycle to match on. 0 = write cycle will be matched 1 = read cycle w ill be matched
development support breakpoints mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor development support 401 these bits are used to compare against the most significant byte of the address bus. these bits are used to compare against the least significant byte of the address bus. these bits may be exclud ed from being used in the match if bk0ale = 0. table 19-11. breakpoint read/write control bk1rwe bk1rw bk0rwe bk0rw read/write selected ??0xr/w is don?t care for full mode or dual mode bkp0 ??10r/w is write for full mode or dual mode bkp0 ??11r/w is read for full mode or dual mode bkp0 0x??r/w is don?t care for dual mode bkp1 10??r/w is write for dual mode bkp1 11??r/w is read for dual mode bkp1 bit 7654321bit 0 bit 15 14 13 12 11 10 9 bit 8 reset: 0 0 0 0 0 0 0 0 brkah ? breakpoint address register, high byte $0022 bit 7654321bit 0 bit 7654321bit 0 reset: 0 0 0 0 0 0 0 0 brkal ? breakpoint address register, low byte $0023
development support technical data mc68hc9 12d60a ? rev. 3.1 402 development support freescale semiconductor these bits are compared to the most significant byte of the data bus or the most significant by te of the address bus in dual address modes. bken[1:0], bkdbe, and bkmbh control how this byte will be used in the breakpoint comparison. these bits are compared to the least significant byte of the data bus or the least significant by te of the address bus in dual address modes. bken[1:0], bkdbe, bk1ale , and bkmbl control how this byte will be used in the break point comparison. 19.6 instruction tagging the instruction queue and cycle-by-cycle cpu activity can be reconstructed in real ti me or from trace histor y that was captured by a logic analyzer. howeve r, the reconstructed queue cannot be used to stop the cpu at a specific instruct ion, because exec ution has already begun by the time an op eration is visible outsi de the mcu. a separate instruction tagging me chanism is provided for this purpose. executing the bdm taggo command configures two mcu pins for tagging. the taglo signal shares a pin with the lstrb signal, and the bit 7654321bit 0 bit 15 14 13 12 11 10 9 bit 8 reset: 0 0 0 0 0 0 0 0 brkdh ? breakpoint data register, high byte $0024 bit 7654321bit 0 bit 7654321bit 0 reset: 0 0 0 0 0 0 0 0 brkdl ? breakpoint data register, low byte $0025
development support technical data mc68hc9 12d60a ? rev. 3.1 403 development support freescale semiconductor tag h i signal shares a pin with the bkgd signal. tagging information is latched on the falling edge of eclk. table 19-12 shows the functions of t he two tagging pins. the pins operate independently - the st ate of one pin does not affect the function of the other. th e presence of logic le vel zero on either pi n at the fall of eclk performs the indica ted function. tagging is allowed in all modes. tagging is disabled when bdm becom es active and bdm serial commands are not processed while tagging is active. the tag follows program information as it advances through the queue. when a tagged instruction reache s the head of t he queue, the cpu enters active background debugging mo de rather than execute the instruction. table 19-12. tag pin function taghi taglo tag 1 1 no tag 1 0 low byte 0 1 high byte 0 0 both bytes
development support technical data mc68hc9 12d60a ? rev. 3.1 404 development support freescale semiconductor
mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor electrical specifications 405 technical data ? mc68hc912d60a section 20. electrical specifications 20.1 contents 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 20.3 tables of data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 20.2 introduction this section contains the most accurate electric al information for the mc68hc912d60a microcontro ller. this is a 16-bi t device available in two package options, 80-pin qfp and 112-pin tqfp. on-chip peripherals include a 16-bit central processing unit (cpu12), 60k bytes of flash eeprom, 2k bytes of ram, 1k bytes of eeprom, two asynchronous serial communication inte rfaces (sci), a serial peripheral interface (spi), an enhanced captur e timer (ect), two (one on 80qfp) 8-channel,10-bit analog-to-digital converters (atd), a four-channel pulse-width modulator (p wm), and a can 2.0 a, b software compatible module (mscan12).
electrical specifications technical data mc68hc9 12d60a ? rev. 3.1 406 electrical specifications freescale semiconductor 20.3 tables of data table 20-1. maximum ratings (1) 1. permanent damage can occur if maximu m ratings are exceeded. exposures to voltages or currents in excess of recom- mended values affects device reliability. device modules may not operate normally while being exposed to electrical ex- tremes. rating symbol value unit supply voltage v dd , v dda , v ddx, v ddpll ? 0.3 to + 6.5 v input voltage v in ? 0.3 to + 6.5 v operating temperature range mc912d60xcpv8 mc912d60xvpv8 mc912d60xmpv8 (single chip mode only) t a t l to t h ? 40 to + 85 ?40 to +105 ?40 to +125 c operating temperature range mc912d60xcfu8 mc912d60xvfu8 mc912d60xmfu8 (single chip mode only) t a t l to t h ? 40 to + 85 ?40 to +105 ?40 to +125 c storage temperature range t stg ? 55 to + 150 c current drain per pin (2) excluding v dd and v ss 2. one pin at a time, observing maximum power dissipation limits. internal circuitry protects the inputs against damage caused by high static voltages or electric fields; however, normal precautions are necessary to avoid application of any voltage higher than maximum-rated voltages to this high-impedance ci rcuit. extended operation at the maximum ratings can ad- versely affect device reliability. tying unused inputs to an appropriate logic voltage level (either gnd or v dd ) enhances reliability of operation. i in 25 ma v dd differential voltage v dd ? v ddx 6.5 v
electrical specifications tables of data mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor electrical specifications 407 table 20-2. thermal characteristics characteristic symbol value unit average junction temperature t j t a + (p d ja ) c ambient temperature t a user-determined c package thermal resistance (junction-to-ambient) 80-pin quad flat pack (qfp) ja 50 c/w package thermal resistance (junction-to-ambient) 112-pin thin quad flat pack (tqfp) ja 51 c/w total power dissipation (1) p d p int + p i/o or w device internal power dissipation p int i dd v dd w i/o pin power dissipation (2) p i/o user-determined w a constant (3) k p d (t a + 273 c) + ja p d 2 w c 1. this is an approximate value, neglecting p i/o . 2. for most applications p i/o ? p int and can be neglected. 3. k is a constant pertaining to th e device. solve for k with a known t a and a measured p d (at equilibrium). use this value of k to solve for p d and t j iteratively for any value of t a . k t j 273 c + ------------------------- -
electrical specifications technical data mc68hc9 12d60a ? rev. 3.1 408 electrical specifications freescale semiconductor table 20-3. dc elect rical characteristics v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted characteristic symbol min max unit input high voltage, all inputs v ih 0.7 v dd v dd + 0.3 v input low voltage, all inputs v il v ss ? 0.3 0.2 v dd v output high voltage, all i/o and output pins except xtal normal drive strength i oh = ? 10.0 a i oh = ? 0.8 ma reduced drive strength i oh = ? 4.0 a i oh = ? 0.3 ma v oh v dd ? 0.2 v dd ? 0.8 v dd ? 0.2 v dd ? 0.8 ? ? ? ? v v v v output low voltage, all i/o and output pins except xtal normal drive strength i ol = 10.0 a i ol = 1.6 ma reduced drive strength i ol = 3.6 a i ol = 0.6 ma v ol ? ? ? ? v ss + 0.2 v ss + 0.4 v ss + 0.2 v ss + 0.4 v v v v input leakage current v in = v dd or v ss all input only pins except atd (1) and v fp v in = v dd or v ss i in ? ? 2.5 10 a a three-state leak age, i/o ports, bkgd, and reset i oz ? 2.5 a input capacitance all input pins and atd pins (non-sampling) atd pins (sampling) all i/o pins c in ? ? ? 10 15 20 pf pf pf output load capacitance all outputs except ps[7:4] ps[7:4] when configured as spi c l ? ? 90 200 pf pf programmable active pull-up current xirq , irq , dbe , lstrb , r/w , ports a, b, can, p,s, t moda, modb active pull down during reset bkgd passive pull up i apu 50 50 50 500 500 500 a a a 1. see table 20-5 .
electrical specifications tables of data mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor electrical specifications 409 table 20-4. supply current v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted characteristic symbol frequency of operation (e-clock) unit 2 mhz (1) 4 mhz (1) 8 mhz maximum total supply current run: single-chip mode expanded mode i dd 18 30 30 50 50 85 ma wait: (all peripheral functions shut down) (2) single-chip mode expanded mode w idd 4 5 6 9 8 12 ma stop: (2) single-chip mode, no clocks ? 40 to + 85 + 85 to + 105 + 105 to + 125 s idd 10 50 50 10 50 50 10 50 50 a a a maximum power dissipation (3) single-chip mode expanded mode p d 100 165 165 275 275 467 mw 1. for information only. supply current guaranteed at 8mhz only. 2. on the 80 qfp package option, unbonded pins must be made outputs or have pullups enabled. 3. includes i dd and i dda . table 20-5. atd dc electrical characteristics v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , atd clock = 2 mhz , unless otherwise noted characteristic symbol min max unit analog supply voltage v dda 4.5 5.5 v analog supply current, normal operation (1) i dda 1.0 ma reference voltage, low v rl v ssa v dda / 2 v reference voltage, high v rh v dda / 2v dda v v ref differential reference voltage v rh ? v rl 4.5 5.5 v input voltage (2) v indc v ssa v dda v input current, off channel (3) i off 100 na reference supply current i ref 250 a input capacitancenot sampling sampling c inn c ins 10 15 pf pf 1. for each atd module. 2. to obtain full-scale, full-range results, v ssa v rl v indc v rh v dda . 3. maximum leakage occurs at maximum operating temperature. current decreases by approximately one-half for each 10 c decrease from maximum temperature.
electrical specifications technical data mc68hc9 12d60a ? rev. 3.1 410 electrical specifications freescale semiconductor table 20-6. analog converte r characteristics (operating) v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , atd clock = 2 mhz , unless otherwise noted characteristic symbol min typical max unit 8-bit resolution (1) 1 count 20 mv 8-bit absolute error ,(2) 2, 4, 8, and 16 atd sample clocks ae ? 1 + 1 count 10-bit resolution (1) 1 count 5 mv 10-bit absolute error (2) 2, 4, 8, and 16 atd sample clocks ae ?2.5 2.5 count 1. at v rh ? v rl = 5.12v, one 8-bit count = 20 mv, and one 10-bit count = 5mv. 2. these values include quantization error which is inherently 1/2 count for any a/d converter. absolute errors only guaranteed when v rl =v ss , v rh =v dd and when external source impedence is close to zero. table 20-7. atd ac characteristics (operating) v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , atd clock = 2 mhz , unless otherwise noted characteristic sym bol min max unit mcu clock frequency (p-clock) f pclk 2.0 8.0 mhz atd operating clock frequency f atdclk 0.5 2.0 mhz atd 8-bit conversion period clock cycles (1) conversion time (2) n conv8 t conv8 18 9 32 16 cycles s atd 10-bit conversion period clock cycles (1) conversion time (2) n conv10 t conv10 20 10 34 17 cycles s stop and atd power up recovery time (3) vdda = 5.0v t sr 10 s 1. the minimum time assumes a final sample period of 2 atd clock cycles wh ile the maximum time assumes a final sample period of 16atd clocks. 2. this assumes an atd clock frequency of 2.0mhz. 3. from the time adpu is asserted unt il the time an atd conversion can begin.
electrical specifications tables of data mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor electrical specifications 411 . table 20-8. atd maximum ratings characteristic symbol value units atd reference voltage v rh v dda v rl v ssa v rh v rl ? 0.3 to + 6.5 ? 0.3 to + 6.5 v v v ss differential voltage | v ss ? v ssa | 0.1 v v dd differential voltage v dd ? v dda v dda ? v dd 6.5 0.3 v v reference to supply differential voltage v dda ? v rh v rh ? v dda v dda ? v rl v rl ? v dda 6.5 0.3 6.5 0.3 v analog input differential voltage v dda ? v indc v indc ? v dda 6.5 0.3 v table 20-9. eeprom characteristics v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted characteristic symbol min max unit minimum programming clock frequency f prog 250k hz programming time t prog 10 ms clock recovery time, following stop, to continue programming t crstop t prog + 1 ms erase time t erase 10 ms write/erase endurance 10,000 cycles data retention 10 (1) years eeprom programming maximum time to ?auto? bit set ? ? 500 s eeprom erasing maximum time to ?auto? bit set ? ? 10 ms 1. based on the average life ti me operating temperature of 70 c.
electrical specifications technical data mc68hc9 12d60a ? rev. 3.1 412 electrical specifications freescale semiconductor table 20-10. flash eeprom characteristics v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted characteristic symbol min max units bytes per row ? 64 64 bytes read bus clock frequency f read 32k 8m hz erase time t eras 88ms pgm/eras to hven set up time t nvs 10 ? s high voltage hold time t nvl 5? s high voltage hold time (erase) t nvhl 100 ? s program hold time t pgs 5? s program time t fpgm 30 40 s return to read time t rcv 1? s cumulative program hv period t hv ?8ms row program/erase endurance ? 100 cycles data retention ? 10 (1) years 1. based on the average life time operating temperature of 70 c. table 20-11. pulse width modulator characteristics v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted characteristic symbol min max unit eclk frequency f eclk 0.004 8.0 mhz a-clock frequency selectable f aclk f eclk /128 f eclk hz bclk frequency selectable f bclk f eclk /128 f eclk hz left-aligned pwm frequency 8-bit 16-bit f lpwm f eclk /1m f eclk /256m f eclk /2 f eclk /2 hz hz left-aligned pwm resolution r lpwm f eclk /4k f eclk hz center-aligned pwm frequency 8-bit 16-bit f cpwm f eclk /2m f eclk /512m f eclk f eclk hz hz center-aligned pwm resolution r cpwm f eclk /4k f eclk hz
electrical specifications tables of data mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor electrical specifications 413 note: reset is recognized during t he first clock cycle it is held low. internal circuitry then drives the pin low for 16 clock cycles, releases the pin, and samples the pin level 9 cycles late r to determine the source of the interrupt. table 20-12. control timing characteristic symbol 8.0 mhz unit min max frequency of operation f o 0.004 8.0 mhz eclk period t cyc 0.125 250 s external oscillator frequency f eo 0.5 16.0 (1) mhz processor control setup time t pcsu = t cyc / 2 + 20 t pcsu 82.5 ? ns reset input pulse width to guarantee external reset vector minimum input time (can be preempted by internal reset) pw rstl 32 2 ? ? t cyc t cyc mode programming setup time t mps 4? t cyc mode programming hold time t mph 10 ? ns interrupt pulse width, irq edge-sensitive mode pw irq = 2t cyc + 20 pw irq 270 ? ns wait recovery startup time t wrs ?4 t cyc timer input capture pulse width pw tim = 2t cyc + 20 pw tim 270 ? ns 1. when using a quartz crystal, see table 20-17 for allowable values.
electrical specifications technical data mc68hc9 12d60a ? rev. 3.1 414 electrical specifications freescale semiconductor figure 20-1. timer inputs pt7 2 pt7 1 pt[7:0] 2 pt[7:0] 1 notes : 1. rising edge sensitive input 2. falling edge sensitive input pw tim pw pa
electrical specifications tables of data mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor electrical specifications 415 figure 20-2. por and exter nal reset timing diagram t pcsu internal moda, modb eclk extal v dd reset 4098 t cyc free fffe fffe 3rd 1st 2nd free fffe fffe fffe t mph pw rstl t mps address pipe pipe pipe 1st exec 3rd pipe 2nd pipe 1st pipe 1st exec note: reset timing is subject to change.
electrical specifications technical data mc68hc9 12d60a ? rev. 3.1 416 electrical specifications freescale semiconductor figure 20-3. stop r ecovery timing diagram pw irq t stopdelay 3 irq 1 irq or xirq eclk 1st address 4 sp-9 free free vector free free resume program with instruction which follows the stop instruction. internal address 5 clocks notes: 1. edge sensitive irq pin (irqe bit = 1) 2. level sensitive irq pin (irqe bit = 0) 3. t stopdelay = 4098 t cyc if dly bit = 1 or 2 t cyc if dly = 0. 4. xirq with x bit in ccr = 1. 5. irq or (xirq with x bit in ccr = 0). opt 1st 2nd 3rd 1st exec pipe pipe exec sp-8 sp-6 fetch pipe sp-6 sp-8 sp-9
electrical specifications tables of data mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor electrical specifications 417 figure 20-4. wait r ecovery timing diagram t pcsu pc, iy, ix, b:a, , ccr stack registers eclk r/w address irq , xirq , or internal interrupts sp ? 2 sp ? 4 sp ? 6 . . . sp ? 9 sp ? 9 sp ? 9 . . . sp ? 9 sp ? 9 vector free 1st 2nd 3rd pipe t wrs note: reset also causes recovery from wait. address pipe pipe 1st exec
electrical specifications technical data mc68hc9 12d60a ? rev. 3.1 418 electrical specifications freescale semiconductor figure 20-5. interrupt timing diagram eclk pw irq 1st 3rd address irq 1 sp ? 9 t pcsu irq 2 , xirq , or internal interrupt vector sp ? 2 1st sp ? 4 sp ? 6 2nd sp ? 8 data vect pc iy ix b:a ccr prog r/w notes: 1. edge sensitive irq pin (irqe bit = 1) 2. level sensitive irq pin (irqe bit = 0) fetch addr exec pipe pipe pipe prog fetch prog fetch
electrical specifications tables of data mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor electrical specifications 419 figure 20-6. port read timing diagram figure 20-7. port write timing diagram table 20-13. peripheral port timing characteristic symbol 8.0 mhz unit min max frequency of operation (eclk frequency) f o 0.004 8.0 mhz eclk period t cyc 0.125 250 s peripheral data setup time mcu read of portst pdsu = t cyc / 2 + 40 t pdsu 102 ? ns peripheral data hold time mcu read of ports t pdh 0?ns delay time, peripheral data write mcu write to ports except port can t pwd ?40ns delay time, peripheral data write mcu write to port can t pwd ?71ns eclk mcu read of port ports t pdsu t pdh eclk mcu write to port previous port data new data valid port a t pwd
electrical specifications technical data mc68hc9 12d60a ? rev. 3.1 420 electrical specifications freescale semiconductor table 20-14. multiplex ed expansion bus timing v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted num characteristic (1), (2), (3), (4) delay symbol 8 mhz unit min max frequency of operation (eclk frequency) f o 0.004 8.0 mhz 1 cycle timet cyc = 1 / f o ? t cyc 0.125 250 s 2 pulse width, e lowpw el = t cyc / 2 + delay ? 4 pw el 58 ns 3 pulse width, e high (5) pw eh = t cyc / 2 + delay ? 2 pw eh 60 ns 5 address delay timet ad = t cyc / 4 + delay 27 t ad 50 ns 7 address valid time to eclk riset av = pw el ? t ad ? t av 8ns 8 multiplexed address hold timet mah = t cyc / 4 + delay ? 18 t mah 13 ns 9 address hold to data valid ? t ahds 20 ns 10 data hold to high zt dhz = t ad ? 20 ? t dhz 30 ns 11 read data setup time ? t dsr 25 ns 12 read data hold time ? t dhr 0ns 13 write data delay time ? t ddw 47 ns 14 write data hold time ? t dhw 20 ns 15 write data setup time (5) t dsw = pw eh ? t ddw ? t dsw 13 ns 16 read/write delay timet rwd = t cyc / 4 + delay 18 t rwd 49 ns 17 read/write valid time to e riset rwv = pw el ? t rwd ? t rwv 9ns 18 read/write hold time ? t rwh 20 ns 19 low strobe (6) delay timet lsd = t cyc / 4 + delay 18 t lsd 49 ns 20 low strobe (6) valid time to e riset lsv = pw el ? t lsd ? t lsv 9ns 21 low strobe (6) hold time ? t lsh 20 ns 22 address access time (5) t acca = t cyc ? t ad ? t dsr ? t acca 50 ns 23 access time from e rise (5) t acce = pw eh ? t dsr ? t acce 35 ns 24 dbe delay from eclk rise (5) t dbed = t cyc / 4 + delay 8 t dbed 39 ns 25 dbe valid timet dbe = pw eh ? t dbed ? t dbe 21 ns 26 dbe hold time from eclk fall t dbeh 010ns 1. all timings are calculated for normal port drives. 2. crystal input is required to be within 45% to 55% duty. 3. reduced drive must be off to meet these timings. 4. unequalled loading of pins will affect relative timing numbers. 5. this characteristic is affected by clock stretch. add n t cyc where n = 0, 1, 2, or 3, depending on the number of clock stretches. 6. without tag enabled.
electrical specifications tables of data mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor electrical specifications 421 figure 20-8. multiplexed expansion bus timing diagram dbe 24 25 eclk r/w 1 2 3 18 11 12 14 note: measurement points shown are 20% and 70% of v dd 13 16 17 read write 23 lstrb 21 19 20 (w/o tag enabled) 5 7 22 8 15 address/data multiplexed address address data data 10 9 26
electrical specifications technical data mc68hc9 12d60a ? rev. 3.1 422 electrical specifications freescale semiconductor table 20-15. spi timing (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , 200 pf load on all spi pins) (1) num function symbol min max unit operating frequency master slave f op f eclk /256 f eclk /256 4 4 mhz 1 sck period master slave t sck 2 2 256 ? t cyc t cyc 2 enable lead time master slave t lead 1 / 2 1 ? ? t sck t cyc 3 enable lag time master slave t lag 1 / 2 1 ? ? t sck t cyc 4 clock (sck) high or low time master slave t wsck t cyc ? 30 t cyc ? 30 128 t cyc ? ns ns 5 sequential transfer delay master slave t td 1 / 2 1 ? ? t sck t cyc 6 data setup time (inputs) master slave t su 30 30 ? ? ns ns 7 data hold time (inputs) master slave t hi 0 30 ? ? ns ns 8 slave access time t a ?1 t cyc 9 slave miso disable time t dis ?1 t cyc 10 data valid (after sck edge) master slave t v ? ? 50 50 ns ns 11 data hold time (outputs) master slave t ho 0 0 ? ? ns ns 12 rise time input output t ri t ro ? ? t cyc ? 30 30 ns ns 13 fall time input output t fi t fo ? ? t cyc ? 30 30 ns ns 1. all ac timing is shown with respect to 20% v dd and 70% v dd levels unless otherwise noted.
electrical specifications tables of data mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor electrical specifications 423 a) spi master ti ming (cpha = 0) b) spi master ti ming (cpha = 1) figure 20-9. spi timing diagram (1 of 2) sck (output) sck (output) miso (input) mosi (output) ss 1 (output) 1 10 6 7 msb in 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 11 4 4 2 10 (cpol = 0) (cpol = 1) 5 3 12 13 1. ss output mode (dds7 = 1, ssoe = 1). 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. sck (output) sck (output) miso (input) mosi (output) 1 6 7 msb in 2 bit 6 . . . 1 lsb in master msb out 2 master lsb out bit 6 . . . 1 4 4 10 12 13 11 port data (cpol = 0) (cpol = 1) port data ss 1 (output) 5 2 13 12 3 1. ss output mode (dds7 = 1, ssoe = 1). 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb.
electrical specifications technical data mc68hc9 12d60a ? rev. 3.1 424 electrical specifications freescale semiconductor a) spi slave timing (cpha = 0) b) spi slave timing (cpha = 1) figure 20-10. spi timi ng diagram (2 of 2) sck (input) sck (input) mosi (input) miso (output) ss (input) 1 10 6 7 msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 11 4 4 2 8 (cpol = 0) (cpol = 1) 5 3 13 note: not defined but normally msb of character just received. slave 13 12 11 see 12 note 9 sck (input) sck (input) mosi (input) miso (output) 1 6 7 msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 4 4 10 12 13 11 see (cpol = 0) (cpol = 1) ss (input) 5 2 13 12 3 note: not defined but normally lsb of character just received. slave note 8 9
electrical specifications tables of data mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor electrical specifications 425 table 20-16. cgm characteristics v dd = 5.0 v dc 10%, v ss = 0 v dc, t a = t l to t h characteristic symbol min. typ. max. unit pll reference frequency f ref 0.5 8 mhz bus frequency f bus 0.004 8 mhz vco range f vco 2.5 8 mhz vco limp-home frequency f vcomin 0.5 1 2.5 (1) mhz lock detector transition from acquisition to tracking mode (2) ? trk 3% 4% ? lock detection ? lock 0% 1.5% ? un-lock detection ? unl 0.5% 2.5% ? lock detector transition from tracking to acquisition mode (2) ? unt 6% 8% ? minimum leakage resistan ce on crystal oscillator pins r leak 1m ? on the k38k mask set pll stabilization delay (3) pll total stabilization delay (4) t stab 3ms pllon acquisition mode stabilization delay. (4) t acq 1ms pllon tracking mode stabilization delay. (4) t al 2ms 1. on the k38k mask set, the limp home mode freq uency is higher than the specified maximum limit. 2. auto bit set 3. pll stabilization delay is highly dependent on operational re quirement and external component values (i.e. crystal, xfc filter component values|). note (4) shows typical delay values for a typical c onfiguration. appropri ate xfc filter values should be chosen ba sed on operational requirement of system. 4. f ref = 4mhz, f bus = 8mhz (refdv = #$00, synr = #$01), xf c:cs = 33nf, cp = 3.3nf, rs = 2.7k ? . table 20-17. oscillator characteristics mc68hc912d60a mc68hc912d60c mc68hc912d60p unit input buffer hysteresis (1) min max 0 50 75 350 75 350 mv resonator frequency (2) (vddpll=vdd) min max 0.5 8 0.5 8 0.5 8 mhz resonator frequency (2) (vddpll=0v) min max 4 10 4 10 0.5 16 mhz 1. these values are dervied from design simulation and are not tested 2. specifications apply to quartz or ceramic resonators only
electrical specifications technical data mc68hc9 12d60a ? rev. 3.1 426 electrical specifications freescale semiconductor table 20-18. key wake-up v dd = 5.0v dc 10%, v ss = 0 vdc, t a = t l to t h characteristic symbol min. max. unit stop key wake-up filter time t kwstp 210 s key wake-up single pulse time interval t kwsp 20 s table 20-19. mscan12 wake- up time from sleep mode v dd = 5.0v dc 10%, v ss = 0 vdc, t a = t l to t h, unless otherwise noted characteristic symbol min. max. unit wake-up time t wup 25 s
mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor appendix: cgm practical aspects 427 technical data ? mc68hc912d60a section 21. appendix: cgm practical aspects 21.1 contents 21.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 21.3 practical aspects for the pll usage . . . . . . . . . . . . . . . . . . 427 21.4 printed circuit board gui delines. . . . . . . . . . . . . . . . . . . . . . . 433 21.2 introduction this sections provides useful and practical pieces of information concerning the implement ation of the cgm module. 21.3 practical aspects for the pll usage 21.3.1 synthesized bus frequency starting from a cera mic resonator or quartz crystal frequency f xtal , if ?refdv? and ?synr? are the decima l content of the refdv and synr registers respectively , then the mcu bus freque ncy will simply be: note: it is not allowed to synthesize a bus frequency that is lower than the crystal frequency, as the correc t functioning of some internal f bus f vco f xtal synr 1 + () ? refdv 1 + () -------------------------- --------------------- - == synr 0,1,2,3...63} { refdv 0,1,2,3...7} {
appendix: cgm practical aspects technical data mc68hc9 12d60a ? rev. 3.1 428 appendix: cgm practical aspects freescale semiconductor synchronizers would be jeopardiz ed (e.g. the mclk and xclk clock generators). 21.3.2 operation under adver se environmental conditions the normal operation for t he pll is the so-called ?automatic bandwidth selection mode? wh ich is obtained by having t he auto bit set in the pllcr register. when this mode is selected and as the vco frequency approaches its target, the charge pump current level will automatically switch from a relative ly high value of around 40 a to a lower value of about 3 a. it can happen that this low level of c harge pump current is not enough to overcome leakages present at the xfc pin due to adverse environmental conditions . these conditions ar e frequently encountered for uncoated pcbs in automotive applications . the main symptom for this failure is an unstable characterist ic of the pll which in fact ?hunts? between acquisition and tracking m odes. it is then advised for the running software to place the pll in manual, forced acquisition mode by clearing both the auto and the acq bits in the pll cr register. doing so will maintain the hi gh current level in the c harge pump constantly and will permit to sustain higher levels of leakages at the xfc pin. this latest revision of the clock generator module mainta ins the lock detection feature even in manual bandwidth control, offering then to the application software the same flexibi lity for the clocking control as the automatic mode. 21.3.3 filter compon ents selection guide 21.3.3.1 equations set these equations can be used to select a set of filter components. two cases are considered: 1. the ?tracking? mode. this situation is reac hed normally when the pll operates in automatic bandwidth selection mode (auto=1 in the pllcr register). 2. the ?acquisition? mode. this sit uation is reached when the pll operates in manual bandwidth selection mode and forced
appendix: cgm practical aspects practical aspects for the pll usage mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor appendix: cgm practical aspects 429 acquisition (auto=0, acq =0 in the pllcr register). in both equations, the power supply should be 5v. st art with the target loop bandwidth as a function of t he other parameters, but obviously, nothing prevents the user from starting with t he capacitor value for example. also, remember that the smoothing capacitor is always assumed to be one tenth of t he series capacitance value. so with: m: the multiplying factor for the reference frequency (i.e. (synr+1)) r: the series resistance of the low pass filter in ? c: the series capacitance of the low pass filter in nf f bus : the target bus freque ncy expressed in mhz : the desired damping factor f c : the desired loop bandwidth expressed in hz for the ?tracking? mode: and for the ?acquisition? mode: 21.3.3.2 particular ca se of an 8mhz synthesis assume that a desired value for the damping factor of the second order system is close to 0.9 as this leads to a satisfactory transient response. then, derived from t he equations above, table 21-1 and table 21-2 suggest sets of values corres ponding to several loop bandwidth possibilities in the case of an 8mhz synthesis for the two cases mentioned above. f c 210 9 2 ?? rc ?? ------------------------- 37.78 e 1.675 f bus ? 10.795 ----------------------------- ?? ?? r ?? 2 m ?? ----------------------------------------------------- - == f c 210 9 2 ?? rc ?? ------------------------- 415.61 e 1.675 f bus ? 10.795 ----------------------------- ?? ?? r ?? 2 m ?? -------------------------------------------------------- - ==
appendix: cgm practical aspects technical data mc68hc9 12d60a ? rev. 3.1 430 appendix: cgm practical aspects freescale semiconductor the filter components values are chos en from standard series (e.g. e12 for resistors). the operating voltage is assumed to be 5v (although there is only a minor difference between 3v and 5v operati on). the smoothing capacitor cp in parallel with r and c is set to be 1/10 of the value of c. the reference frequencies mentioned in this table correspond to the output of the fine granularity divider controll ed by the refdv register. this means that the calculations are irrespective of the way the reference frequency is gene rated (directly for the crystal oscillator or after division). the target frequency va lue also has an influence on the calculations of the filter compo nents because the vco gain is not constant over its operating range. the bandwidth limit corresponds to the so-called gardner? s criteria. it corresponds to the maximum value that can be chosen before the continuous time approximation ceases to be justified. it is of course advisable to stay far away from this limit.
appendix: cgm practical aspects practical aspects for the pll usage mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor appendix: cgm practical aspects 431 table 21-1. suggested 8mhz synthesis pll filter elements (tracking mode) reference [mhz] synr fbus [mhz] c [nf] r [k ? ] loop bandwidth [khz] bandwidth limit [khz] 0.614 $0c 7.98 100 4.3 1.1 157 0.614 $0c 7.98 4.7 20 5.3 157 0.614 $0c 7.98 1 43 11.5 157 0.614 $0c 7.98 0.33 75 20 157 0.8 $09 8.00 220 2.7 0.9 201 0.8 $09 8.00 10 12 4.2 201 0.8 $09 8.00 2.2 27 8.6 201 0.8 $09 8.00 0.47 56 19.2 201 1 $07 8.00 220 2.4 1 251 1 $07 8.00 10 11 4.7 251 1 $07 8.00 2.2 24 9.9 251 1 $07 8.00 0.47 51 21.4 251 1.6 $05 8.00 330 1.5 1 402 1.6 $05 8.00 10 9.1 5.9 402 1.6 $05 8.00 3.3 15 10.2 402 1.6 $05 8.00 1 27 18.6 402 2 $03 8.00 470 1.1 0.96 502 2 $03 8.00 22 5.1 4.4 502 2 $03 8.00 4.7 11 9.6 502 2 $03 8.00 1 24 20.8 502 2.66 $02 8.00 220 1.5 1.6 668 2.66 $02 8.00 22 4.7 5.1 668 2.66 $02 8.00 4.7 10 11 668 2.66 $02 8.00 1 22 24 668 4 $01 8.00 220 1.2 1.98 1005 4 $01 8.00 33 3 5.1 1005 4 $01 8.00 10 5.6 9.3 1005 4 $01 8.00 2.2 12 19.8 1005
appendix: cgm practical aspects technical data mc68hc9 12d60a ? rev. 3.1 432 appendix: cgm practical aspects freescale semiconductor table 21-2. suggested 8mhz synthesis pll filter elements (acquisition mode) reference [mhz] synr fbus [mhz] c [nf] r [k ? ] loop bandwidth [khz] bandwidth limit [khz] 0.614 $0c 7.98 1000 0.43 1.2 157 0.614 $0c 7.98 47 2 5.5 157 0.614 $0c 7.98 10 4.3 12 157 0.614 $0c 7.98 3.3 7.5 21 157 0.8 $09 8.00 2200 0.27 0.9 201 0.8 $09 8.00 100 1.2 4.4 201 0.8 $09 8.00 22 2.4 9.3 201 0.8 $09 8.00 4.7 5.6 20.1 201 1 $07 8.00 2200 0.22 1 251 1 $07 8.00 100 1 4.8 251 1 $07 8.00 2. 2.2 10.4 251 1 $07 8.00 4.7 4.7 22.5 251 1.6 $05 8.00 3300 0.15 1.1 402 1.6 $05 8.00 100 0.82 6.2 402 1.6 $05 8.00 33 1.5 10.7 402 1.6 $05 8.00 10 2.7 19.5 402 2 $03 8.00 4700 0.1 1 502 2 $03 8.00 220 0.51 4.6 502 2 $03 8.00 47 1 10 502 2 $03 8.00 10 2.4 21.8 502 2.66 $02 8.00 2200 0.12 1.7 668 2.66 $02 8.00 220 0.43 5.3 668 2.66 $02 8.00 47 1 11.6 668 2.66 $02 8.00 10 2 25.1 668 4 $01 8.00 2200 0.1 2.1 1005 4 $01 8.00 330 0.27 5.4 1005 4 $01 8.00 100 0.51 9.7 1005 4 $01 8.00 22 1 20.8 1005
appendix: cgm practical aspects printed circuit board guidelines mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor appendix: cgm practical aspects 433 21.4 printed circuit board guidelines printed circuit boards (pcbs) ar e the board of choice for volume applications. if designed correctly, a very low noise system can be built on a pcb with consequently good em i/emc performanc es. if designed incorrectly, pcbs can be extremel y noisy and sensitive modules, and the cgm could be disrupted. some common sense rules can be used to prevent such problems. use a ?star? style power routing plan as opposed to a ?daisy chain?. route power and ground from a c entral location to each chip individually, and use the widest trac e practical (the more the chip draws current, the wider the trace). never pl ace the mcu at the end of a long string of se rially connected chips. when using pcb layout software, fi rst direct the routing of the power supply lines as we ll as the cgm wires (c rystal oscillator and pll). layout constraints must be then reported on the other signals and not on these ?hot? nodes. optimizing the ?hot? nodes at the end of the rout ing process usually gives bad results. avoid notches in power trac es. these notches not only add resistance (and are not usually a ccounted for in simulations), but they can also add unnecessa ry transmission line effects. avoid ground and power loops. this has been one of the most violated guidelines of pcb layout. loops are excellent noise transmitters and can be easily avoid ed. when using multiple layer pcbs, the power and ground plane concept wo rks well but only when strictly adhered to (do not compromise the ground plane by cutting a hole in it and running si gnals on the ground plane layer). keep the spacing around via holes to a minimum (but not so small as to add capacitive effects). be aware of the three dimensio nal capacitive effects of multi- layered pcbs. bypass (decouple) the power suppli es of all chips as close to the chip as possible. use one dec oupling capacitor per power supply pair (vdd/vss, vddx/ vssx...). two capacitor s with a ratio of about 100 sometimes offer better performances over a broader
appendix: cgm practical aspects technical data mc68hc9 12d60a ? rev. 3.1 434 appendix: cgm practical aspects freescale semiconductor spectrum. this is especially the case for the power supply pins close to the e port, w hen the eclk and/or the calibration clock are used. on the general vdd power supply input, a ?t? low pass filter lcl can be used (e.g. 10 h-47 f-10 h). the ?t? is pref erable to the ? ? version as the ex hibited impedance is more constant with respect to the vdd curr ent. like many modular micro controllers, hc12 devices have a power consum ption which not only varies with clock edges but also with the functioning modes. keep high speed clock and bus trace length to a minimum. the higher the clock spe ed, the shorter the tr ace length. if noisy signals are sent over long tra cks, impedance adjustments should be considered at both ends of the line (generally, simple resistors suffice). bus drivers like the can physica l interface should be installed close to their connector, with dedi cated filtering on their power supply. mount components as close to t he board as possible. snip excess lead length as close to the board as poss ible. preferably use surface mount devices (smds). mount discrete components as close to the chip that uses them as possible. do not cross sensitive signals on any layer. if a sensitive signal must be cross ed by another signal, do it as many layers away as possible a nd at right angles. always keep pcbs clea n. solder flux, oils from fingerprints, humidity and general dirt can conduct electricity. sensitive circuits can easily be disrupted by small amounts of leakage. choose pcb coatings with care. certain epoxies, paints, gelatins, plastics and waxes can conduct electr icity. if the manufacturer cannot provide the electr ical characteristics of the substance, do not use it.
appendix: cgm practical aspects printed circuit board guidelines mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor appendix: cgm practical aspects 435 in addition to the a bove general pieces of advice, the following guidelines should be followed for the cgm pins (but also more generally for any sensitive analog circuitry): parasitic capacitance on extal is absolutely critical ? probably the most critical layo ut consideration. the xtal pin is not as sensitive. all routi ng from the extal pin through the resonator and the blocking cap to the actual connecti on to vss must be considered. for minimum capacitance there should ideally be no ground / power plane around the extal pin and associated routing. however, practical emc considerat ions obviously should be taken into consideration for each application. the clock input circuitry is sensit ive to noise so excellent supply routing and decoupling is mandato ry. connect the ground point of the oscillator circuit dire ctly to the vsspll pin. good isolation of p ll / oscillator power supply is critical. use 1nf+ 100nf and keep tracks as low impedance as possible load capacitors should be lo w leakage and stable across temperature ? use npo or c0g types. the load capacitors may ?pull? th e target frequency by a few ppm. crystal manufacturer specs show symmetrical values but the series device capacitance on extal and xtal are not symmetrical. it may be possible to adjust this by changing the values of the load capacitors ? start-up conditions should be evaluated. keep the adjacent port h / po rt e and reset si gnals noise free. don?t connect these to external si gnals and / or add series filtering ? a series resistor is probably adequate. any dc-blocking capacitor should be as low esr as possible ? for the range of crystals we are lookin g at anything over 1 ohm is too much. mount oscillator components on m cu side of board ? avoid using vias in the oscillator circuitry.
appendix: cgm practical aspects technical data mc68hc9 12d60a ? rev. 3.1 436 appendix: cgm practical aspects freescale semiconductor mount the pll filter and oscill ator components as close to the mcu as possible. do not allow the extal and xtal signals to interfere with the xfc node. keep these tra cks as short as possible. do not cross the cgm signals with any other signal on any level. remember that the reference vo ltage for the xfc filter is vddpll. as the return path for the oscillat or circuitry is vsspll, it is extremely important to connect vsspll to v ss even if the pll is not to be powered. surf ace mount components reduce the susceptibility of si gnal contamination.
mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor appendix : changes from mc68hc912d60 437 technical data ? mc68hc912d60a section 22. appendix: changes from mc68hc912d60 22.1 contents 22.2 significant changes from the mc68hc912d60 (non-suffix device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 22.2.1 flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 22.2.2 eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 22.2.3 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 22.2.4 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 22.2.5 kwu filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .440 22.2.6 port adx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 22.2.7 atd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 22.2 significant changes from th e mc68hc912d60 (non-suffix device) 22.2.1 flash 22.2.1.1 flash architecture the flash arrays are made from a new non-volatile memory (nvm) technology. an external vfp is no longer used. programming is now carried out on a whole row (64 bytes) at a time. erasing is still a bulk erase of the entire array. 22.2.1.2 flash control register the flash control register (feectl) is in the sa me location. however, the individual bit functi ons have changed significant ly to support the new technology.
appendix: changes from mc68hc912d60 technical data mc68hc9 12d60a ? rev. 3.1 438 appendix: changes from mc68hc912d60 freescale semiconductor 22.2.1.3 flash programming procedure programming of the flash is greatly simplified ov er previous hc12s. the read / verify / re-pulse programming algorithm is replaced by a much simpler method. 22.2.1.4 flash programming time the most significant change resulting from the new flash technology is that the bulk erase and pr ogram times are now fix ed. the erase time is at least twice as fast while the word programming time is at least 20% faster. 22.2.1.5 flash extern al programming voltage the new flash does not require an ex ternal high volt age supply. all voltages required for programmi ng and erase are now generated internally. pin 97 (112 qfp) or pin 71 (80 qfp) is now a test pin for the flash arrays. applying 12 v to this pin can damage the device. on early production devices it is recommended that this pin is not connected within the application, but it may be connected to vss or 5.5v max without issue. 22.2.2 eeprom 22.2.2.1 eeprom architecture like the flash, the eeprom is also made from this new nvm technology. the architecture and basic programming and erase operations are unchanged. howeve r, there is a new optional programming method that allows faster progr amming of the eeprom. 22.2.2.2 eeprom clock source and pre-scaler the first major difference on the ne w eeprom is that it requires a constant time base source to ensure secure programming and erase operations. the clock source that is going to driv e the clock divider input is the external clock i nput, extali. the divide rati o from this source has
appendix: changes from mc68hc912d60 significant changes from the mc68hc912d60 (non-suffix device) mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor appendix : changes from mc68hc912d60 439 to be set by programming an 10-bit time base pre-sca lar into bits spread over two new register s, eedivh and eedivl. the eedivh and eedivl regi sters are volatile. however, they are loaded upon reset by the contents of the non-volatile shadow word much in the same wa y as the eeprom modul e control register (eemcr) bits interact wi th the shadow word fo r configuration control on the existing revision. 22.2.2.3 eeprom auto programming & erasing the second major change to the eepr om is the inclusion in the eeprom control register (eeprog) of an aut o function using the previously unused bit 5 of this register. the auto function enables the logic of the mcu to automatically use the optimum programming or erasing time for the eeprom. if using auto, the user does not need to wa it for the normal minimum specified programming or erasing time. after se tting the eepgm bi t as normal the user just has to poll that bit agai n, waiting for the mcu to clear it indicating that programming or erasing is complete. 22.2.2.4 eeprom sele ctive write more zeros for some applications it may be adv antageous to track more than 10k events with a single byte of eeprom by programmi ng one bit at a time. for that purpose, a special sele ctive bit programmi ng technique is available. when this technique is ut ilized, a program / er ase cycle is defined as multiple writes (up to eight) to a unique locati on followed by a single erase sequence. 22.2.3 stop mode this new version will correctly ex it stop mode wi thout having to synchronize the start of stop with the rti clock.
appendix: changes from mc68hc912d60 technical data mc68hc9 12d60a ? rev. 3.1 440 appendix: changes from mc68hc912d60 freescale semiconductor 22.2.4 wait mode this new version will correctly exit wait mode using s hort xirq or irq inputs. 22.2.5 kwu filter the kwu filter will now ignore pulses shorte r than 2 microseconds. 22.2.6 port adx power must be applied to vdda at all times even if the adc is not being used. this is necessary for port ad0 and port ad1 to function correctly as digital inputs. this is also valid for mc68hc912d60. 22.2.7 atd 22.2.7.1 channel selection any channel can be selected for the first conversion of a multiple channel conversion. bits ca, cb & cc in at dxctl5 do not get masked but are used to select which channel is us ed to start the s equential conversion sequence. for compatibilty, ensure that the appropriate bits are cleared in the software. see table 18-8 . 22.2.7.2 cd bit bit cd in atdxctl5 is renamed sc to differentiate it from extended functionality of bits ca, cb & cc. functionality is unchanged as it still selects conversion from th e internal reference sources but when doing a multiple channel scan, bi ts ca, cb & cc must be cleared as appropriate for compatible reference selection.
appendix: changes from mc68hc912d60 significant changes from the mc68hc912d60 (non-suffix device) mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor appendix : changes from mc68hc912d60 441 22.2.7.3 additional features atd flexibility has been increased with additional si gned result, data justification, single conversion selection and results location fifo features. the djm bit has been added to atdxctl2 register. default values are compatible with mc68h c912d60 functionality. fifo & s1c bits have been added to at dxctl3 register. default values are compatible with mc 68hc912d60 functionality. 22.2.7.4 s8cm bit bit s8cm in atdxctl5 is renamed s8c. functionality is compatible with s8cm but can now be modified by the new s1c bit in atdxctl3. the default is compatible with mc68hc912d60 functionality. 22.2.7.5 awai bit bit awai in atdxctl2 is r enamed aswai, com patible with m68hc912dt128a. funct ionality is unchanged. 22.2.7.6 writi ng to atdxctl4 writing to atdxctl4 aborts any ongoing conversion sequence and initiates a new conversion sequence. previously it onl y aborted ongoing sequences leaving the atd in idle mode ( no conversion sequences being processed). writing to atdx ctl2 or adtxctl3 also does not abort an ongoing conversion sequence. previously writing these registers also aborted an y ongoing sequence leav ing the atd in idle mode . this is unlikely to be a compatibility issue as appl ications mostly write these registers to conf igure the atd, closely followed by a write to atdxctl5 to initiate a new conver sion sequence which does abort any ongoing conversion sequence and rese ts the appropriate flags.
appendix: changes from mc68hc912d60 technical data mc68hc9 12d60a ? rev. 3.1 442 appendix: changes from mc68hc912d60 freescale semiconductor to ensure compatibility, the applic ation should not rely on ongoing conversions being aborted. also any interrupts from the completion of an ongoing sequence should be masked and/or handled correctly. 22.2.7.7 scf bit in scan mode (sc an bit = 1 in atdxctl5) the sequence complete flag (scf bit in atdstatx) is se t after completion of each conversion sequence. previously it was only set at the end of the first conversion sequence. to ensure compatibility the application should not rely on this flag being set only once per scan mode. 22.2.7.8 atdtestx reading the atdtestx register in nor nal modes returns the value of the successive approximation register (sar). previous ly it always read as zero. the rst bit in the atdtestx regist er can be written in normal modes (in order to reset the atd). previously it was read only. to ensure compatibility this register should not be r ead or written to.
mc68hc912d60a ? rev. 3.1 technical data freescale semiconductorappendix: information on mc68hc912d60a mask set changes 443 technical data ? mc68hc912d60a section 23. appendix: information on mc68hc912d60a mask set changes 23.1 contents 23.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 23.3 flash protection feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 23.4 clock circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 23.5 pseudo stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 23.6 oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .444 23.7 pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 23.2 introduction the following changes have been made on the mc68hc912d60a from the 2k38k mask set to the 1l02h mask set. further improvements were made to t he oscillator circuit to create the 2l02h mask set (mc68hc912d 60c) and the 3l02h mask set (mc68hc912d60p). thes e are described in detai l in the oscillator section of this document. 23.3 flash prot ection feature a flash protection bit has been added to the eemcr register to protect the flash memory from accidental progr am or erasure. this bit is loaded from the eeprom s hadow word at reset, so that the flash can be protected before any software is executed. see eeprom and flash sectio ns for more details.
appendix: information on mc68hc912d60a mask technical data mc68hc9 12d60a ? rev. 3.1 444 appendix: information on mc68hc912d60a mask set changes freescale semiconduc- 23.4 clock circuitry the crystal oscillator output is now frozen when limp home (lh) mode is entered to prevent rapid switching between crystal and lh clocks. improvements have been made to the bus clock switching circuitry to eliminate the potential fo r glitches to appear on the internal clock line. the duration of the clo ck monitor pulses was increased to reduce sensitivity of the cl ock monitor circuit to short clock pulses. 23.5 pseudo stop mode oscillator amplifier drive is now not reduced in pseudo stop mode. when exiting pseudo stop mode, the device will now not go into limp home mode since the cryst al is already running. 23.6 oscillator the automatic level control (alc) capacitor reference was changed from vdd to vss in the crystal oscillator circuit to improve noise immunity. parasitic capacitance on internal si gnal lines has been decreased, thus decreasing sensitivity to ex ternal capacitance changes. note: for best oscillator performance, it is recommended that the load capacitor selection is verifi ed on changing to the 1l02h mask. a reduction was made to the gain of the operat ional transconductance amplifier (ota) to reduce the amplif ication of any noise on the extal pin. this is a small in cremental improvement.
appendix: information on mc68hc912d60a mask set changes pll mc68hc912d60a ? rev. 3.1 technical data freescale semiconductorappendix: information on mc68hc912d60a mask set changes 445 23.7 pll the limp home clock fre quency has been re-alligned to the specification values to reduce sensitivity to system noise and hence reduce pll jitter. note: it is advisable to verify the xfc filter co mponents and pll lock time due to the above changes. vco start-up will now be at the minimum frequen cy whilst the power up sequence of the curr ent controlled oscillator has been improved. the xfc pin is now preconditioned to vddpll when pll is deselected so xfc doesn?t float. this ensures th e pll starts up at low frequency and ramps up to th e desired frequency.
appendix: information on mc68hc912d60a mask technical data mc68hc9 12d60a ? rev. 3.1 446 appendix: information on mc68hc912d60a mask set changes freescale semiconduc-
mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor glossary 447 technical data ? mc68hc912d60a glossary a ? see ?accumulators (a and b or d).? accumulators (a and b or d) ? two 8-bit (a and b) or one 16-bit (d) gener al-purpose registers in the cpu. the cpu uses the accumulators to hold operands and results of arithmetic and logic operations. acquisition mode ? a mode of pll operati on with large loop bandwidth . also see ?tracking mode?. address bus ? the set of wires that the cpu or dma uses to r ead and write memory locations. addressing mode ? the way that the c pu determines the operand address for an instruction. the m68hc12 cpu has 15 addressing modes. alu ? see ?arithmetic logic unit (alu).? analogue-to-digital converter (atd) ? the atd module is an 8- channel, multip lexed-input successive-approximation anal og-to-digital converter. arithmetic logic unit (alu) ? the portion of the cpu that contains the logic circuitry to perform arithmetic, logic, and mani pulation operat ions on operands. asynchronous ? refers to logic circuits and operati ons that are not synch ronized by a common reference signal. atd ? see ?analogue-to-d igital converter?. b ? see ?accumulators (a and b or d).? baud rate ? the total number of bits tr ansmitted per unit of time. bcd ? see ?binary-co ded decimal (bcd).? binary ? relating to the base 2 number system. binary number system ? the base 2 number system, havin g two digits, 0 and 1. binary arithmetic is convenient in digital circ uit design because digital circuits have two permissible voltage levels, lo w and high. the binary digits 0 and 1 can be interpreted to correspond to the two di gital voltage levels.
glossary technical data mc68hc9 12d60a ? rev. 3.1 448 glossary freescale semiconductor binary-coded decimal (bcd) ? a notation that uses 4-bit bi nary numbers to represent the 10 decimal digits and that reta ins the same positional struct ure of a decimal number. for example, 234 (decimal) = 0010 0011 0100 (bcd) bit ? a binary digit. a bit has a valu e of either logic 0 or logic 1. branch instruction ? an instruction that causes the cpu to continue processing at a memory location other than the next sequential address. break module ? the break module allows software to halt program execution at a programmable point in order to enter a background routine. breakpoint ? a number written into th e break address registers of the break module. when a number appears on the internal address bus that is the same as the number in the break address registers, the cpu executes the software in terrupt instruction (swi). break interrupt ? a software interrupt caused by the appearance on the internal address bus of the same value that is written in the br eak address registers. bus ? a set of wires that transfers logic signals. bus clock ? see "cpu clock". byte ? a set of eight bits. can ? see "scalable can." ccr ? see ?condition code register.? central processor unit (cpu) ? the primary functi oning unit of any computer system. the cpu controls the execution of instructions. cgm ? see ?clock generator module (cgm).? clear ? to change a bit from logic 1 to logic 0; the opposite of set. clock ? a square wave signal used to synchronize events in a computer. clock generator module (cgm) ? the cgm module generates a base clock signal from which the system clocks are derived. the cgm may include a crystal o scillator circuit and/or phase-locked loop (pll) circuit. comparator ? a device that compares t he magnitude of two inputs. a digital co mparator defines the equality or relati ve differences between two binary numbers.
glossary mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor glossary 449 computer operating prop erly module (cop) ? a counter module th at resets the mcu if allowed to overflow. condition code register (ccr) ? an 8-bit register in the cpu that contai ns the interrupt mask bit and five bits that i ndicate the results of the instruction just executed. control bit ? one bit of a register m anipulated by software to c ontrol the operation of the module. control unit ? one of two major units of the cpu. the control unit c ontains logic functions that synchronize the machine and direct various operations . the control unit decodes instructions and generates the internal control signals that perform the requested operations. the outputs of the control unit drive the ex ecution unit, which contains the arithmetic logic unit (alu), c pu registers, and bus interface. cop ? see "computer operati ng properly module (cop)." cpu ? see ?central proc essor unit (cpu).? cpu12 ? the cpu of t he mc68hc12 family. cpu clock ? bus clock select bits bcsp and bcss in the clock se lect register (clksel) determine which clock drives sysclk for the main system , including the cpu and buses. when extali drives the sysclk, th e cpu or bus clock frequency (f o ) is equal to the extali frequency divided by 2. cpu cycles ? a cpu cycle is one period of the internal bus clock, normally derived by dividing a crystal oscillator source by two or more so the high and low time s will be equal. the length of time required to execute an in struction is measured in cpu clock cycles. cpu registers ? memory locations that ar e wired directly into the cpu logic inst ead of being part of the addressabl e memory map. the cpu always has dire ct access to the information in these registers. th e cpu registers in an m68hc12 are: a (8-bit accumulator) b (8-bit accumulator) ? d (16-bit accumulator formed by co ncatenation of accumulators a and b) ix (16-bit index register) iy (16-bit index register) sp (16-bit stack pointer) pc (16-bit program counter) ccr (8-bit condit ion code register)
glossary technical data mc68hc9 12d60a ? rev. 3.1 450 glossary freescale semiconductor cycle time ? the period of the op erating frequency: t cyc =1/f op . d ? see ?accumulators (a and b or d).? decimal number system ? base 10 numbering system that us es the digits zero through nine. duty cycle ? a ratio of the amount of time the signal is on versus t he time it is off. duty cycle is usually represented by a percentage. ect ? see ?enhanced capture timer.? eeprom ? electrically erasable, programmable, read-only me mory. a nonvolatile type of memory that can be electrica lly erased and reprogrammed. eprom ? erasable, programmable, read-only memory. a nonvolatile type of memory that can be erased by exposure to an ultraviolet light source a nd then reprogrammed. enhanced capture timer (ect) ? the hc12 enhanced capture time r module has the features of the hc12 standard timer modul e enhanced by additional featur es in order to enlarge the field of applications. exception ? an event such as an inte rrupt or a reset that stops th e sequential execution of the instructions in the main program. fetch ? to copy data from a memory location into the accumulator. firmware ? instructions and data program med into nonvolatile memory. free-running counter ? a device that counts from zero to a predeter mined number, then rolls over to zero and begins counting again. full-duplex transmission ? communication on a channel in which data can be sent and received simultaneously. hexadecimal ? base 16 numbering system that uses the digits 0 through 9 and the letters a through f. high byte ? the most significant eight bits of a word. illegal address ? an address not within the memory map illegal opcode ? a nonexistent opcode. index registers (ix and iy) ? two 16-bit registers in th e cpu. in the indexed addressing modes, the cpu uses the content s of ix or iy to determine the effective address of the operand. ix and iy can also serve as a temporary data storage locations.
glossary mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor glossary 451 input/output (i/o) ? input/output interfaces between a computer system and the external world. a cpu reads an input to sense the level of an external signal and writes to an output to change the level on an external signal. instructions ? operations that a cpu can perform. instructions ar e expressed by programmers as assembly language mnemon ics. a cpu interprets an opcode and its associated operand(s) and instruction. inter-ic bus (i 2 c) ? a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange bet ween devices. interrupt ? a temporary break in the sequential execution of a pr ogram to respond to signals from peripheral devices by executing a subroutine. interrupt request ? a signal from a peripheral to the cpu intended to cause the cpu to execute a subroutine. i/o ? see ?input/output (i/0).? jitter ? short-term signal instability. latch ? a circuit that retain s the voltage level (logic 1 or logic 0) written to it for as long as power is applied to the circuit. latency ? the time lag between instruct ion completion and data movement. least significant bit (lsb) ? the rightmost digit of a binary number. logic 1 ? a voltage level approx imately equal to the input power voltage (v dd ). logic 0 ? a voltage level approximately equal to the gr ound voltage (v ss ). low byte ? the least significant eight bits of a word. m68hc12 ? a freescale family of 16-bit mcus. mark/space ? the logic 1/logic 0 conv ention used in formatting dat a in serial communication. mask ? 1. a logic circuit t hat forces a bit or gro up of bits to a desired st ate. 2. a photomask used in integrated circuit fabricati on to transfer an image onto silicon. mcu ? microcontroller unit. see ?microcontroller.?
glossary technical data mc68hc9 12d60a ? rev. 3.1 452 glossary freescale semiconductor memory location ? each m68hc12 memory location holds one byte of data and has a unique address. to store information in a memory location, the cpu places the address of the location on the address bus, the data information on the dat a bus, and asserts the write signal. to read informat ion from a memory lo cation, the cpu places the address of the location on the address bus and asserts the read signal. in respons e to the read signal, the selected memory location plac es its data onto the data bus. memory map ? a pictorial representati on of all memory locations in a computer system. mi-bus ? see "freescale interconnect bus". microcontroller ? microcontroller unit (mcu). a comp lete computer system, including a cpu, memory, a clock oscillato r, and input/output (i/o) on a single integrated circuit. modulo counter ? a counter that can be programmed to count to any number from zero to its maximum possible modulus. most significant bit (msb) ? the leftmost digi t of a binary number. freescale interconnect bus (mi-bus) ? the freescale interconnec t bus (mi bus) is a serial communications protocol which supports distributed real-time control efficiently and with a high degree of noise immunity. freescale scalable c an (mscan) ? the scalable controller area network is a serial communications protocol that ef ficiently supports distributed real-time control with a very high level of data integrity. mscan ? see "scalable can". msi ? see "multiple serial interface". multiple seri al interface ? a module consisting of multiple independent serial i/o sub-systems, e.g. two sci and one spi. multiplexer ? a device that can select one of a number of inputs and pass the logic level of that input on to the output. nibble ? a set of four bi ts (half of a byte). object code ? the output from an assembler or compil er that is itself executable machine code, or is suitable for processing to produce executable machine code. opcode ? a binary code that instructs the cpu to perform an operation. open-drain ? an output that has no pullup transisto r. an external pu llup device can be connected to the power supply to provide the logic 1 output voltage.
glossary mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor glossary 453 operand ? data on which an operati on is performed. usually a statement consists of an operator and an operand. for exam ple, the operator may be an add instruction, and the operand may be the qu antity to be added. oscillator ? a circuit that produces a constant frequency square wa ve that is used by the computer as a timing and sequencing reference. otprom ? one-time programmable read-only memo ry. a nonvolatile ty pe of memory that cannot be reprogrammed. overflow ? a quantity that is too large to be contained in one byte or one word. page zero ? the first 256 bytes of memory (addresses $0000?$00ff). parity ? an error-checking scheme that counts the nu mber of logic 1s in each byte transmitted. in a system that uses odd parity, every byte is expec ted to have an odd number of logic 1s. in an even parit y system, every byte should have an even number of logic 1s. in the transmitter, a parity generator appends an extra bit to each by te to make the number of logic 1s odd for odd parity or even for even parity. a parity checker in the receiver counts the number of logic 1s in each byte. the parity checker generates an error signal if it finds a byte with an incorrect number of logic 1s. pc ? see ?program counter (pc).? peripheral ? a circuit not under direct cpu control. phase-locked loop (pll) ? a clock generator circ uit in which a voltage controlled oscillator produces an oscillation which is syn chronized to a reference signal. pll ? see "phase-locked loop (pll)." pointer ? pointer register. an index register is sometimes called a pointer register because its contents are used in the calcul ation of the address of an oper and, and theref ore points to the operand. polarity ? the two opposite logi c levels, logic 1 and logic 0, wh ich correspond to two different voltage levels, v dd and v ss . polling ? periodically reading a st atus bit to monitor the c ondition of a peripheral device. port ? a set of wires for communica ting with off-chip devices. prescaler ? a circuit that generates an output signal related to the input signal by a fractional scale factor such as 1/2, 1/8, 1/10 etc. program ? a set of computer instruct ions that cause a computer to perform a desi red operation or operations.
glossary technical data mc68hc9 12d60a ? rev. 3.1 454 glossary freescale semiconductor program counter (pc) ? a 16-bit register in the cpu. the pc r egister holds the address of the next instruction or operand that the cpu will use. pull ? an instruction that copies into the accu mulator the contents of a stack ram location. the stack ram address is in the stack pointer. pullup ? a transistor in the output of a logic gate th at connects the output to the logic 1 voltage of the power supply. pulse-width ? the amount of ti me a signal is on as opposed to being in its off state. pulse-width modulation (pwm) ? controlled variation (modulati on) of the pulse width of a signal with a constant frequency. push ? an instruction that copies the contents of the accumulator to the stack ram. the stack ram address is in the stack pointer. pwm period ? the time required for one comp lete cycle of a pwm waveform. ram ? random access memory. all ram locations can be read or written by the cpu. the contents of a ram memory location remain vali d until the cpu writes a different value or until power is turned off. rc circuit ? a circuit consisting of capacitors and resistors having a de fined time constant. read ? to copy the contents of a memo ry location to the accumulator. register ? a circuit that st ores a group of bits. reserved memory location ? a memory location that is used only in special fa ctory test modes. writing to a reserved loca tion has no effect. reading a reserved location returns an unpredictable value. reset ? to force a device to a known condition. sci ? see "serial communicati on interface module (sci)." serial ? pertaining to s equential transmission over a single line. serial communications inte rface module (sci) ? a module that supp orts asynchronous communication. serial peripheral inte rface module (spi) ? a module that su pports synchronous communication. set ? to change a bit from logic 0 to logic 1; opposite of clear.
glossary mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor glossary 455 shift register ? a chain of circuits that c an retain the logic levels (log ic 1 or logic 0) written to them and that can shift the logic levels to the right or left th rough adjacent ci rcuits in the chain. signed ? a binary number notation that accommodates both po sitive and negative numbers. the most significant bit is us ed to indicate whet her the number is po sitive or negative, normally logic 0 for positive and logic 1 for negative. the other seven bits indicate the magnitude of the number. software ? instructions and data that control the operati on of a microcontroller. software interrupt (swi) ? an instruction that causes an interrupt and its associated vector fetch. spi ? see "serial pe ripheral interfac e module (spi)." stack ? a portion of ram reserved fo r storage of cpu regi ster contents and subroutine return addresses. stack pointer (sp) ? a 16-bit register in the cpu containing the address of the next available storage location on the stack. start bit ? a bit that signals t he beginning of an asynchronous serial transmission. status bit ? a register bit t hat indicates the condition of a device. stop bit ? a bit that signals th e end of an asynchron ous serial transmission. subroutine ? a sequence of instructions to be used more than once in the course of a program. the last instruction in a subrout ine is a return from subrouti ne (rts) instruct ion. at each place in the main program where the subrouti ne instructions are needed, a jump or branch to subroutine (jsr or bsr) in struction is used to call the subroutine. the cpu leaves the flow of the main program to execute the instructions in the subroutine. when the rts instruction is executed, t he cpu returns to the main program where it left off. synchronous ? refers to logic circuits and operati ons that are synchr onized by a common reference signal. timer ? a module used to relate events in a system to a point in time. toggle ? to change the state of an output from a logic 0 to a logic 1 or from a logic 1 to a logic 0. tracking mode ? a mode of pll operation with narro w loop bandwidth. also see ?acquisition mode.?
glossary technical data mc68hc9 12d60a ? rev. 3.1 456 glossary freescale semiconductor two?s complement ? a means of performing bi nary subtraction using addi tion techniques. the most significant bit of a tw o?s complement number indicate s the sign of the number (1 indicates negative). the two?s complement negative of a num ber is obtained by inverting each bit in the number and then adding 1 to the result. unbuffered ? utilizes only one regist er for data; new data ov erwrites current data. unimplemented memory location ? a memory location that is not used. writing to an unimplemented location has no effect. reading an unimple mented location returns an unpredictable value. variable ? a value that changes during t he course of program execution. vco ? see "voltage-controlled oscillator." vector ? a memory location that co ntains the address of the beginni ng of a subroutine written to service an interrupt or reset. voltage-controlled oscillator (vco) ? a circuit that pr oduces an oscillating output signal of a frequency that is c ontrolled by a dc voltage ap plied to a control input. waveform ? a graphical representation in which the amplitude of a wa ve is plotted against time. wired-or ? connection of circuit outputs so that if an y output is high, t he connection point is high. word ? a set of two bytes (16 bits). write ? the transfer of a byte of data from the cpu to a memory location.
mc68hc912d60a ? rev. 3.1 technical data freescale semiconductor revision history 457 technical data ? mc68hc912d60a revision history 23.8 contents 23.9 changes from rev 2.0 to rev 3.0 . . . . . . . . . . . . . . . . . . . . . 457 23.10 major changes from rev 1.0 to rev 2.0 . . . . . . . . . . . . . . . . 457 23.11 major changes from rev 0.0 to rev 1.0 . . . . . . . . . . . . . . . . 458 23.9 changes from rev 2.0 to rev 3.0 23.10 major changes fr om rev 1.0 to rev 2.0 section page (in rev 3.0) description of change eeprom 110 note referring to bit 6 of shadow word has been modified. section page (in rev 2.0) description of change mc68hc912d60c and mc68hc912d60p devices added to document. general description 27 order numbers added for mc68hc912d60c and mc68hc912d60p devices pinout and signal descriptions 38 , 40 45 50 note about test pin updated note added about consideration of crystal selection due to emc emissions description of test pin added as new section and to table 3-2 description of extal an d xtal modified in table 3-2 . registers 64 , 69 68 dsgn bit removed from atd0ctl2/atd1ctl2 registers fpopen bit added to eemcr register flash memory 98 new paragraph added to overview about flash protection via fpopen bit 104 new section 7.11 flash protection bit fpopen added
revision history technical data mc68hc9 12d60a ? rev. 3.1 458 revision history freescale semiconductor 23.11 major changes fr om rev 0.0 to rev 1.0 the advance information data book was converted to technical data book status. this constitu ted only a change of cover. eeprom memory 110 , 111 fpopen bit added to eemcr register clock functions 139 note added about consideration of crystal selection due to emc emissions oscillator new section mscan controller 317 first two bullets of sleep mode description updated 331 slprq = 1 description updated analog-to-digital converter 350 signed/unsigned removed from result data bullet 352 signed/unsigned reference removed from note 359 , 361 dsgn bit removed from atd0ctl2/atd1ctl2 register diagram and bit descriptions. table 18-1 and table 18-2 updated accordingly 376 dsgn bit references removed from adr0-15 description electrical specifications 411 reference to supply differential voltage values updated. v ref differential voltage row removed analog input differential voltage row added 413 f xtal removed 413 footnote added restricting extern al oscillator oper ating frequency to 8mhz when using a quartz crystal 425 table footnote removed from table 20-16 regarding v ddpll appendix: changes from mc68hc912d60 438 sentence removed from end of paragraph in flash external programming voltage . 441 dsgn reference removed from additional features . appendix: cgm practical aspects 427 section 21.3 a few hints for the cgm crystal oscillator application removed. all po ints are covered in new oscillator section. 435 extra bullets added appendix: information on mc68hc912d60a mask set changes new section section page (in rev 2.0) description of change

how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. the arm powered logo is a registered trademark of arm limited. arm7tdmi-s is a trademark of arm limited. java and all other java-based marks are trademarks or registered trademarks of sun microsystems, inc. in the u.s. and other countries. the bluetooth trademarks are owned by their proprietor and used by freescale semiconductor, inc. under license. ? freescale semiconductor, inc. 2005. all rights reserved. rev. 3.1 mc68hc912d60a/d august 17, 2005

▲Up To Search▲

Price & Availability of MC912D60PVFU8

	To Download MC912D60PVFU8 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .